Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: An electronic contact lens. In some embodiments, the electronic contact lens includes: a power management circuit; and a first cell, the power management circuit including an active switch, the active switch being configured to isolate the first cell from other contact lens elements when the power management circuit is powered down.

Abstract: An electronic contact lens. In some embodiments, the electronic contact lens includes: a receiver, including: a voltage-controlled oscillator; a phase-alignment circuit, connected to a control input of the voltage-controlled oscillator; and an offset-compensating circuit, connected to the control input of the voltage-controlled oscillator, the receiver being configured: to operate in: a calibration mode, or an operating mode; and to select, in the calibration mode, an operating-mode setting of the offset-compensating circuit, the selecting including: adjusting the offset-compensating circuit, and monitoring an output frequency of the voltage-controlled oscillator.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: A micro-LED display has an array of separately controllable micro-LEDs and corresponding pixel drivers. The pixel drivers have pulse-width modulation (PWM) generator circuits for the LEDs. The PWM generator circuits include the following. N input nodes are coupled to receive N control bits that determine a brightness of the LEDs. An output node is coupled to output the drive signal to the LEDs. Each of N transistors are connected between one of the input nodes and the output node. Each transistor is controlled by a clock signal CKn and couples the input node to the output node as controlled by the clock signal CKn.

Abstract: A micro-LED display has an array of separately controllable micro-LEDs and corresponding pixel drivers. The pixel drivers have pulse-width modulation (PWM) generator circuits for the LEDs. The PWM generator circuits include the following. N input nodes are coupled to receive N control bits that determine a brightness of the LEDs. An output node is coupled to output the drive signal to the LEDs. Each of N transistors are connected between one of the input nodes and the output node. Each transistor is controlled by a clock signal CKn and couples the input node to the output node as controlled by the clock signal CKn.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: An electronic contact lens. In some embodiments, the electronic contact lens includes: a receiver, including: a voltage-controlled oscillator; a phase-alignment circuit, connected to a control input of the voltage-controlled oscillator; and an offset-compensating circuit, connected to the control input of the voltage-controlled oscillator, the receiver being configured: to operate in: a calibration mode, or an operating mode; and to select, in the calibration mode, an operating-mode setting of the offset-compensating circuit, the selecting including: adjusting the offset-compensating circuit, and monitoring an output frequency of the voltage-controlled oscillator.

Abstract: An electronic contact lens. In some embodiments, the electronic contact lens includes: a power management circuit; and a first cell, the power management circuit including an active switch, the active switch being configured to isolate the first cell from other contact lens elements when the power management circuit is powered down.

Abstract: An electronic contact lens. In some embodiments, the electronic contact lens includes a plurality of power-consuming circuits and a power supply circuit. The power supply circuit may be configured to distribute available power among two voltage domains in the electronic contact lens according to changing power requirements within the two voltage domains.

Abstract: A contact lens battery management system (BMS) monitors battery health in an electronic contact lens. A battery made with high-internal-resistance cells is coupled on a cell-by-cell basis to input switches of a power management integrated circuit (PMIC) that monitors, detects, and isolates faulty circuit components.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: An electronic contact lens. In some embodiments, the electronic contact lens includes a plurality of power-consuming circuits and a power supply circuit. The power supply circuit may be configured to distribute available power among two voltage domains in the electronic contact lens according to changing power requirements within the two voltage domains.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: A contact lens battery management system (BMS) monitors battery health in an electronic contact lens. A battery made with high-internal-resistance cells is coupled on a cell-by-cell basis to input switches of a power management integrated circuit (PMIC) that monitors, detects, and isolates faulty circuit components.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: A circuit for duty cycle detection and correction, for a serial data transmitter. The circuit includes a pattern generator having a pattern data output configured to be selectively connected to the data input of the serial data transmitter, and a duty cycle detection circuit, connected to the output of the serial data transmitter. The pattern generator is configured to produce a pattern including a sequence including an odd number of consecutive zeros and a same number of consecutive ones. The duty cycle detection circuit is configured to measure a difference between a first interval and a second interval, in a signal at the output of the serial data transmitter, the first interval corresponding to the odd number of consecutive zeros within the sequence and the second interval corresponding to the odd number of consecutive ones within the sequence.

Abstract: A semiconductor memory system includes a first semiconductor memory die and a second semiconductor memory die. The first semiconductor memory die includes a primary data interface to receive an input data stream during write operations and to deserialize the input data stream into a first plurality of data streams, and also includes a secondary data interface, coupled to the primary data interface, to transmit the first plurality of data streams. The second semiconductor memory die includes a secondary data interface, coupled to the secondary data interface of the first semiconductor memory die, to receive the first plurality of data streams.

Abstract: A phase-locked loop circuit comprises a multi-phase oscillator having a plurality of coupled oscillators. A calibration module detects mismatches between frequency characteristics of the different oscillators in the phase-locked loop circuit during a calibration process. The calibration module then calibrates the various oscillators to compensate for the detected mismatch. Once calibrated, the phase-locked loop circuit can operate with little or no performance degradation despite the mismatch in frequency characteristics between the different oscillators.