Patents by Inventor Mohammad Honarparvar
Mohammad Honarparvar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240030932Abstract: Described herein is a fractional phase locked loop with sigma-delta modulator (SDM) quantization noise cancellation. The fractional phase includes a digital filter configured to receive an error signal based on a comparison of a reference clock and a feedback clock, a controlled oscillator configured to generate an output clock by adjusting a frequency of the controlled oscillator based on a control signal output by the digital filter, the feedback clock being based on the output clock, a sigma-delta modulator configured to control division of the output clock to generate a divided output clock which includes a sigma-delta modulator quantization noise and a digital-to-time converter configured to receive a cancellation code from an integrator in the sigma-delta modulator and cancel the sigma-delta modulator quantization noise in the divided output clock with the cancellation code to generate the feedback clock.Type: ApplicationFiled: July 20, 2022Publication date: January 25, 2024Applicant: Ciena CorporationInventors: Tingjun Wen, Sadok Aouini, Naim Ben-Hamida, Matthew Mikkelsen, Soheyl Ziabakhsh Shalmani, Mohammad Honarparvar
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Publication number: 20230412187Abstract: Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.Type: ApplicationFiled: October 29, 2021Publication date: December 21, 2023Inventors: Mohammad Honarparvar, Sadok Aouini, Jerry Yee-Tung Lam, Soheyl Ziabakhsh Shalmani, Naim Ben-Hamida
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Patent number: 11770126Abstract: A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.Type: GrantFiled: September 15, 2020Date of Patent: September 26, 2023Assignee: Ciena CorporationInventors: Mohammad Honarparvar, Soheyl Ziabakhsh Shalmani, Naim Ben-Hamida, Sadok Aouini
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Publication number: 20230208428Abstract: A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.Type: ApplicationFiled: September 15, 2020Publication date: June 29, 2023Inventors: Mohammad Honarparvar, Soheyl Ziabakhsh Shalmani, Naim Ben-Hamida, Sadok Aouini
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Patent number: 11538511Abstract: Described are apparatus and methods for fractional synchronization using direct digital frequency synthesis (DDFS). A DDFS device includes a memory with N address spaces, a write port circuit configured to sequentially write a digital desired pattern into the N address spaces, a read port circuit configured to readout the digital desired pattern from the N address spaces using continuous sequential automatic addressing from 0 to N?1 at a memory operating frequency clock, where the memory operating frequency clock is based on a sampling frequency clock used for high-speed data processing, and an analog signal processing circuit configured to process a readout digital desired pattern into an analog representation; and output a synthesized frequency clock from the analog representation to a digital core, where the synthesized frequency clock is fractionally synchronized with the sampling frequency clock.Type: GrantFiled: February 11, 2021Date of Patent: December 27, 2022Assignee: Ciena CorporationInventors: Soheyl Ziabakhsh Shalmani, Robert Gibbins, Sadok Aouini, Mohammad Honarparvar, Naim Ben-Hamida, Youssef Karmous, Christopher Kurowski
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Publication number: 20220254394Abstract: Described are apparatus and methods for fractional synchronization using direct digital frequency synthesis (DDFS). A DDFS device includes a memory with N address spaces, a write port circuit configured to sequentially write a digital desired pattern into the N address spaces, a read port circuit configured to readout the digital desired pattern from the N address spaces using continuous sequential automatic addressing from 0 to N?1 at a memory operating frequency clock, where the memory operating frequency clock is based on a sampling frequency clock used for high-speed data processing, and an analog signal processing circuit configured to process a readout digital desired pattern into an analog representation; and output a synthesized frequency clock from the analog representation to a digital core, where the synthesized frequency clock is fractionally synchronized with the sampling frequency clock.Type: ApplicationFiled: February 11, 2021Publication date: August 11, 2022Applicant: Ciena CorporationInventors: Soheyl Ziabakhsh Shalmani, Robert Gibbins, Sadok Aouini, Mohammad Honarparvar, Naim Ben-Hamida, Youssef Karmous, Christopher Kurowski
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Patent number: 11196438Abstract: Described are apparatus and methods for analog to digital converter (ADC) with factoring and background clock calibration. An apparatus includes an ADC configured to sample and convert differential input signals using a reference clock to obtain a defined number of samples during a first state in an acquisition clock cycle, and a finite state machine circuit configured to obtain the defined number of samples from the ADC using a clock based on the reference clock, factor the defined number of samples based on at least a common mode offset associated with the ADC, and send offset factored output to a controller.Type: GrantFiled: January 22, 2021Date of Patent: December 7, 2021Assignee: Ciena CorporationInventors: Soheyl Ziabakhsh Shalmani, Hazem Beshara, Mohammad Honarparvar, Sadok Aouini, Christopher Kurowski, Naim Ben-Hamida
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Publication number: 20210359696Abstract: Described are apparatus and methods for analog to digital converter (ADC) with factoring and background clock calibration. An apparatus includes an ADC configured to sample and convert differential input signals using a reference clock to obtain a defined number of samples during a first state in an acquisition clock cycle, and a finite state machine circuit configured to obtain the defined number of samples from the ADC using a clock based on the reference clock, factor the defined number of samples based on at least a common mode offset associated with the ADC, and send offset factored output to a controller.Type: ApplicationFiled: January 22, 2021Publication date: November 18, 2021Applicant: Ciena CorporationInventors: Soheyl Ziabakhsh Shalmani, Hazem Beshara, Mohammad Honarparvar, Sadok Aouini, Christopher Kurowski, Naim Ben-Hamida
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Patent number: 11171664Abstract: Described herein are apparatus and methods for digitally enhancing digital-to-analog converter (DAC) resolution. A digitally enhanced DAC includes a decoder circuit configured to convert a N-bit input data to at least N code bits, a digital enhancement circuit configured to logically operate on a least significant bit (LSB) of the N-bit data, and a switching network including at least N DAC unit elements, where a least significant DAC unit element is controlled by the digital enhancement circuit to output a factored nominal current or voltage when a logical operation outputs a defined logic level for the LSB and to output a nominal current or voltage absent output of the defined logic level and a remaining DAC unit elements are controlled by a remaining code bits of the at least N code bits. This provides a N+1 bit resolution for the DAC without increasing the at least N DAC unit elements.Type: GrantFiled: October 30, 2020Date of Patent: November 9, 2021Assignee: Ciena CorporationInventors: Mohammad Honarparvar, Sadok Aouini, Jerry Yee-Tung Lam, Soheyl Ziabakhsh Shalmani, Naim Ben-Hamida
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Patent number: 10979059Abstract: Described herein are apparatus and methods for a successive approximation register (SAR) analog-to-digital (ADC) based phase-locked loop (PLL) with programmable range. A multi-bit digital phase locked loop includes a multi-bit phase frequency detector configured to output a multi-bit error signal based on a reference clock, a feedback clock sampled using the reference clock, and a threshold voltage, a multi-bit digital low pass filter configured to apply a variable gain to the multi-bit error signal, a current steered digital-to-analog converter configured to generate a control current based on a gain applied multi-bit error signal and multi-bit digital phase locked loop control parameters, a controlled oscillator configured to adjust a frequency of the controlled oscillator based on the control current to generate an output clock, the feedback clock being based on the output clock, and a programmable edge time controller configured to adjust a slope of an edge of the feedback clock.Type: GrantFiled: October 26, 2020Date of Patent: April 13, 2021Assignee: Ciena CorporationInventors: Soheyl Ziabakhsh Shalmani, Sadok Aouini, Matthew Mikkelsen, Hazem Beshara, Tingjun Wen, Mohammad Honarparvar, Naim Ben-Hamida
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Patent number: 10938405Abstract: Described herein are apparatus and methods for low speed characterization of a high-speed signal. A circuit includes a sub-sampling circuit configured to sub-sample a high-speed signal received from a device, a reconstruction loop circuit configured to reconstruct a low-speed signal from the sub-sampled high-speed signal, a low pass filter configured to filter the reconstructed low-speed signal, a discrete time low pass filter configured to mitigate skew rate requirements of the filtered low-speed signal for a digitization circuit, a continuous time low pass filter configured to smooth the skew rate mitigated low-speed signal and the digitization circuit is configured to generate a digital representation of the smoothed low-speed signal for characterization by a characterization device, and shape a noise associated with the smoothed low-speed signal outside a frequency range of interest of the smoothed low-speed signal.Type: GrantFiled: March 18, 2020Date of Patent: March 2, 2021Assignee: Ciena CorporationInventors: Mohammad Honarparvar, Naim Ben-Hamida
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Patent number: 10931292Abstract: Described are apparatus and methods for successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with factoring and background clock calibration. An apparatus includes a SAR ADC configured to, in response to receiving an enable flag based on detection of an acquisition clock with a first logic state sent by a controller, sample and convert a pair of differential input signals using a sampling clock to obtain a defined number of samples in an acquisition clock cycle and a factoring circuit configured to obtain the defined number of samples from the SAR ADC using a capturing clock based on the sampling clock, factor the defined number of samples, and send a factored samples ready flag to the controller.Type: GrantFiled: May 13, 2020Date of Patent: February 23, 2021Assignee: Ciena CorporationInventors: Soheyl Ziabakhsh Shalmani, Hazem Beshara, Mohammad Honarparvar, Sadok Aouini, Christopher Kurowski, Naim Ben-Hamida
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Patent number: 10826514Abstract: A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.Type: GrantFiled: October 15, 2019Date of Patent: November 3, 2020Assignee: Ciena CorporationInventors: Mohammad Honarparvar, Soheyl Ziabakhsh Shalmani, Naim Ben-Hamida, Sadok Aouini
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Patent number: 10715169Abstract: A receiver gain tracking loop utilizing two Digital-to-Analog Converters (DACs) and methods for operating the gain tracking loop are provided. The gain tracking circuit includes a signal detector for detecting at least one signal and outputting a detected signal; a digital integrator connected in series to the signal detector for integrating the detected signal in the digital domain; two DACs connected in parallel to the digital integrator; and an analog summing element for summing the first digital output and the second digital output of the DACs producing a combined output.Type: GrantFiled: May 21, 2019Date of Patent: July 14, 2020Assignee: Ciena CorporationInventors: Sadok Aouini, Tom Luk, Naim Ben-Hamida, Christopher Kurowski, Mohammad Honarparvar, Soheyl Ziabakhsh Shalmani