Abstract: Techniques for forward error correction are disclosed. These techniques include receiving a forward error correction codeword transmitted over a communication network, the codeword including a parity portion and a payload portion. The techniques further include determining, based on the parity portion, to disable forward error correction for the codeword. The techniques further include disabling forward error correction for the codeword.

Abstract: Techniques for forward error correction are disclosed. These techniques include receiving a forward error correction codeword transmitted over a communication network, the codeword including a parity portion and a payload portion. The techniques further include determining, based on the parity portion, to disable forward error correction for the codeword. The techniques further include disabling forward error correction for the codeword.

Abstract: Devices, systems, methods, and processes for transmitting and receiving one or more data packets are described herein. A device may face an internal non-deterministic delay in processing causing a gap or an interruption during transmission of the data packet. During the gap, the device can transmit one or more Intra-Packet Idle (IPI) words between the transmission of the data packet. The IPI words can be ignored or discarded by a receiver. The device may transmit the data packet into multiple parts by transmitting the IPI words between the parts. The receiver can receive the parts of the data packet and the IPI words and retrieve the data packet based on the parts of the data packet. The device may set a configurable threshold value indicative of a maximum number of the IPI words that can be transmitted during the gap of the interruption, such that the receiver can efficiently identify and discard a runt packet.

Abstract: Techniques for forward error correction are disclosed. These techniques include receiving a forward error correction codeword transmitted over a communication network, the codeword including a parity portion and a payload portion. The techniques further include determining, based on the parity portion, to disable forward error correction for the codeword. The techniques further include disabling forward error correction for the codeword.

Abstract: A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank.

Abstract: A device for repairing a memory device may include spare memory blocks that may replace corresponding memory blocks that include at least one non-operational memory cell. One or more registers may be coupled in a chain to store memory repair information. A memory repair module may identify, upon a power-up test of the memory device, non-operational memory cells, which are incremental to previously identified defective memory cells in previous power-up tests, and may provide corresponding memory repair information of the identified non-operational memory cells. A logic circuit may block access to one or more registers and may facilitate storing, in one or more unblocked registers, the corresponding memory repair information of the identified one or more non-operational memory cells. The memory repair module may swap a memory block including the identified non-operational memory cells with a spare memory block based on content of the one or more unblocked registers.

Abstract: A memory device with a logical-to-physical (LTP) bank mapping cache that supports multiple read and write accesses is described herein. The memory device allows for at least one read operation and one write operation to be received during the same clock cycle. In the event that the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation may be stored in the physical memory bank corresponding to a logical memory bank that is associated with the incoming write operation. In the event that the incoming write operation is blocked by the at least one read operation, then data for that incoming write operation may be stored in an unmapped physical bank that is not associated with any logical memory bank.

Abstract: There is provided a system for secure profile setting that includes at least one shared device and an RFID reader module embedded in the at least one shared device. The system further includes a database that is in communication with the at least one shared device. In the system, an RFID transponder module associated with a user transmits a signal that enables the at least one shared device to identify the user. The RFID transponder module can include a fingerprint scanner module, which can be used to acquire a user's fingerprint data to authenticate the user. Thus, after identifying the user, the at least one shared device retrieves a profile corresponding to the user from the database and sets the profile.

Abstract: A network system which includes a plurality of separate processing entities, an input output bus, and a network interface unit shared among the plurality of separate processing entities is disclosed. The network interface unit is coupled to the plurality of separate processing entities via the input output bus. The network interface unit has a plurality of memory access channels and each memory access channel is assigned to one processing entity.

Abstract: There is provided a system for secure profile setting that includes at least one shared device and an RFID reader module embedded in the at least one shared device. The system further includes a database that is in communication with the at least one shared device. In the system, an RFID transponder module associated with a user transmits a signal that enables the at least one shared device to identify the user. The RFID transponder module can include a fingerprint scanner module, which can be used to acquire a user's fingerprint data to authenticate the user. Thus, after identifying the user, the at least one shared device retrieves a profile corresponding to the user from the database and sets the profile.