Abstract: A digitally controlled circuit is arranged to provide the combined functions of level shifting, multiplexing, and delay control functions. The circuit is compact, and uses lower power and lower overall noise susceptibility over other solutions. A programmable bias current is arranged to adjust the delay through the circuit. The bias current can be provided by a digitally controlled current source, a binary weighted current DAC, or other digitally controlled means. The multiplexing functions are provided by an input stage circuit that is current limited by the programmable bias current. An output stage is arranged to convert signals from the input stage to a desired voltage level.

Abstract: A digitally controlled circuit is arranged to provide the combined functions of level shifting, multiplexing, and delay control functions. The circuit is compact, and uses lower power and lower overall noise susceptibility over other solutions. A programmable bias current is arranged to adjust the delay through the circuit. The bias current can be provided by a digitally controlled current source, a binary weighted current DAC, or other digitally controlled means. The multiplexing functions are provided by an input stage circuit that is current limited by the programmable bias current. An output stage is arranged to convert signals from the input stage to a desired voltage level.

Abstract: A data serializer includes a data aligner, two N-bit shift registers, a 2-1 multiplexer, and a driver, wherein N is the number of parallel input data bits. Data is received and aligned by the data aligner, which is arranged to drive odd and even data lines to a respective one of the N-bit shift registers. One N-bit shift register is arranged to operate with a clock that is 180 degrees out of phase with respect to the other N-bit shift register. The frequency of the clock for each N-bit shift register is related to an input clock frequency by a factor of N/2. The multiplexer is arranged to alternate the selection of the N-bit shift registers to provide the output signal. The output of the multiplexer corresponds to a high-speed serial data stream that can be provided to a driver such as LVDS, DVI, PPDS or RSDS drivers.