Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass core having a first opening and a second opening spaced apart from the first opening, the second opening having a greater width than the first opening. The example apparatus further includes a conductive material adjacent a first wall of the first opening; and a dielectric material adjacent a second wall of the second opening.

Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.

Abstract: Techniques for a coaxial inductor in a glass core are disclosed. In an illustrative embodiment, an inductor is positioned in a cavity of a glass core. The inductor includes a conductive via extending through the glass core surrounded by a magnetic material. A buffer layer is positioned between the edges of the cavity of the glass core and the inductor. The buffer can prevent or mitigate any stress caused by changes in temperature and different coefficients of thermal expansion of the glass core and the inductor. The inductor may form part of a fully integrated voltage regulator (FIVR), which provides a stable voltage source to a semiconductor die such as a processor.

Abstract: Coaxial magnetic inductor structures useful for semiconductor packaging applications are provided. The coaxial magnetic inductors can be located in semiconductor package cores and the semiconductor package cores can be, for example, comprised of an amorphous solid glass material. Methods of manufacturing a coaxial magnetic inductors in a package substrate core are also provided.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a glass core layer having a first surface layer and a second surface layer; multiple channels within the glass core layer between the first surface and the second surface layer; and a first redistribution layer (RDL) including multiple sublayers of conductive traces formed in an organic material, wherein a first surface of the RDL contacts the first surface of the glass core layer.

Abstract: Disclosed herein are antenna units, microelectronic assemblies, and communication devices that may enable RF chip-to-chip communications in a compact form factor. An example microelectronic assembly may include a microelectronic component (e.g., a package substrate, a circuit board, and interposer, or a die) and an antenna unit that may be separately fabricated and integrated in a recess in the microelectronic component, enabling increased degrees of design freedom and improved yield. An example antenna unit may include a glass core having a first face and an opposing second face, a tapered opening extending between the first face and the second face of the glass core, and a layer of an electrically conductive material on sidewalls of the opening, where the opening in the glass core lined with the layer of the electrically conductive material forms a horn antenna integrated in the glass core.

Abstract: MEMS dies embedded in glass cores of integrated circuit (IC) package substrates are disclosed. An example integrated circuit (IC) package includes a package substrate including a glass core, the example integrated circuit (IC) package also includes a micro electromechanical system (MEMS) die positioned in a cavity of the glass core.

Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

Abstract: An integrated circuit package comprising an integral structural member embedded within dielectric material and at least partially surrounding a keep-out zone of a co-planar package metallization layer. The integral structural member may increase stiffness of the package without increasing the package z-height. The structural member may comprise a plurality of intersecting elements. Individual structural elements may comprise conductive vias that are non-orthogonal to a plane of the package. An angle of intersection and thickness of the structural elements may be varied to impart more or less local or global rigidity to a package according to a particular package application. Intersecting openings may be patterned in a mask material by exposing a photosensitive material through a half-penta prism. Structural material may be plated or otherwise deposited into the intersecting openings.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, the electronic package comprises a die layer, with a first side and a second side opposite from the first side. In an embodiment, the die layer comprises a first die, and a second die. In an embodiment, a bridge is on the first side of the die layer, where the bridge communicatively couples the first die to the second die. In an embodiment, electrically conductive routing is on the second side of the die layer.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a core with a first surface and a second surface opposite from the first surface, and where the core comprises glass. In an embodiment, a channel is disposed into the first surface of the core, and a lid is provided over the channel. In an embodiment, the lid seals the channel between a first end and a second end of the channel.

Abstract: Embodiments disclosed herein include electronic package packages. In an embodiment, the electronic package comprises a package substrate. In an embodiment, a first die is embedded in the package substrate, and a second die is over the package substrate. In an embodiment, the first die is entirely within a footprint of the second die.

Abstract: A method for identifying a tool anomaly of an printed circuit board (PCB) manufacturing process comprising a plurality of phases, the method comprising the steps of: obtaining image data of at least one tool of the PCB manufacturing process; inputting the image data to a machine learning module, the machine learning module configured to perform the following steps: extracting, from the image data, a tool feature image data of the at least one tool; classifying the image data into a phase of the plurality of phases; and determining, based on the classified image data and the tool feature image data, an anomaly state of the at least one tool.

Abstract: In one embodiment, an integrated circuit package substrate includes a core layer and a plurality of build-up layers on the core layer, each build-up layer comprising a dielectric and metal. The package substrate also includes a cavity, wherein a first portion of the cavity is defined in a first build-up layer, a second portion of the cavity is defined in a second build-up layer, and a third portion of the cavity connects the first portion with the second portion through at least one layer other than first build-up layer and the second build-up layer.

Abstract: Embodiments disclosed herein include an interconnect. In an embodiment, the interconnect comprises a substrate and a pad over the substrate. In an embodiment, a hole is provided through the pad. In an embodiment, the hole exposes a portion of the substrate. In an embodiment, a solder is provided over the pad, and the solder bridges across the hole through the pad.

Abstract: Embodiments disclosed herein include a package core. In an embodiment, the package core comprises a core substrate, a first opening through the core substrate, a second opening through the core substrate and adjacent to the first opening, and a first structure around the core substrate between the first opening and the second opening. In an embodiment, the first structure is electrically conductive. The package core may further comprise a second structure around the core substrate outside of the first opening and the second opening, where the second structure is electrically conductive.

Abstract: Embodiments of a package substrate includes: a conductive via in a first layer, the first layer comprising a positive-type photo-imageable dielectric; a conductive trace in a second layer, the second layer comprising a negative-type photo-imageable dielectric; and an insulative material between the first layer and the second layer, the insulative material configured to absorb electromagnetic radiation in a wavelength range between 10 nanometers and 800 nanometers. The conductive via is directly attached to the conductive trace through the insulative material, the positive-type photo-imageable dielectric is soluble in a photoresist developer upon exposure to the electromagnetic radiation, and the negative-type photo-imageable dielectric is insoluble in the photoresist developer upon exposure to the electromagnetic radiation.

Abstract: Embodiments of a microelectronic assembly includes: a package substrate and an integrated circuit (IC) die coupled to a surface of the package substrate by first interconnects and second interconnects, the first interconnects and the second interconnects comprising solder. The first interconnects are larger than the second interconnects, the first interconnects and the second interconnects further comprise bumps on the IC die and bond-pads on the surface of the package substrate, with the solder coupled to the bumps and the bond-pads, lateral sides of the bumps have a coating of a material that prevents solder wicking, and the surface of the package substrate includes insulative baffles between the bond-pads.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first layer, where the first layer comprises glass, a second layer over the first layer, where the second layer comprises glass, and a third layer over the second layer, where the third layer comprises glass. In an embodiment, a pair of traces are in the second layer, and a first gap is below the pair of traces, where the first gap is in the first layer and the second layer. In an embodiment, a second gap is above the pair of traces, where the second gap is in the second layer and the third layer.