Abstract: A method and type of device for performing passive voltage contrast on a silicon on insulator (SOI) device. A first portion of a substrate of the SOI device may be ground with a dimpler. A second portion of the substrate of the SOI device may be etched using tetramethylammonium hydroxide (TMAH). A third portion of the substrate of the SOI device and a portion of a box insulator of the SOI device may be etched using hydrofluoric (HF) acid. A conductive coating may be applied to the etched portions thereby forming a conductive path from the gate to the substrate if there is a breakdown in the gate oxide. Consequently, the passive voltage contrast technique may be applied to the SOI device to detect a breakdown in the gate oxide which would be illustrated by a bright area in the gate oxide region resulting from the secondary electrons produced.

Abstract: A method and semiconductor device for detecting a heat generating failure in an unpassivated semiconductor device. The semiconductor device has an unpassivated surface and a heat generating failure, e.g., short circuit. A coating may be applied to the unpassivated surface of the semiconductor device. The coating may be non-electrically conducting and capable of localizing heat generated by the failure in a particular area. The semiconductor device may be biased. The failure may then be detected by detecting a location of the heat generated by the failure in the coating.

Abstract: A system and method for removing a conductive line from a semiconductor device is disclosed. The conductive line includes a conductive layer and a barrier layer separating the conductive layer from a portion of the semiconductor device. The method and system include exposing a portion of the barrier layer, etching the barrier layer after the barrier layer has been exposed, and lifting off the conductive layer after the barrier layer has been etched.

Abstract: A method and system for deprocessing a semiconductor device is disclosed. The semiconductor device has a plurality of structures and an intermetal dielectric layer. The method and system include anisotropically plasma etching the intermetal dielectric layer at an oblique angle and rotating the semiconductor device during the plasma etch to reduce or eliminate build up of a material on the plurality of structures due to the plasma etch of the intermetal dielectric layer. In another aspect the method and system include a semiconductor device deprocessed using the method in accordance with the present invention. In another aspect, the present invention includes a system for deprocessing the semiconductor device.

Abstract: An automatic decapsulation system for a device is disclosed. The system comprises an etch plate, an etch head, a sheet coupled to the etch head, a rubber gasket disposed between the etch head and the sheet, and an integrated spacer and protection plate for securing the device without damaging the backside of the device during decapsulation. In one embodiment of the present invention, the integrated spacer and protection plate is adjustable to accommodate devices of varying sizes.

Abstract: A method and system for deprocessing a semiconductor device is disclosed. The semiconductor device has a plurality of structures and an intermetal dielectric layer. The method and system include anisotropically plasma etching the intermetal dielectric layer at an oblique angle and rotating the semiconductor device during the plasma etch to reduce or eliminate build up of a material on the plurality of structures due to the plasma etch of the intermetal dielectric layer. In another aspect the method and system include a semiconductor device deprocessed using the method in accordance with the present invention. In another aspect, the present invention includes a system for deprocessing the semiconductor device.

Abstract: An automatic decapsulation system for a device is disclosed. The system comprises an etch plate, an etch head, a sheet coupled to the etch head, a rubber gasket disposed between the etch head and the sheet, and an integrated spacer and protection plate for securing the device without damaging the backside of the device during decapsulation. In one embodiment of the present invention, the integrated spacer and protection plate is adjustable to accommodate devices of varying sizes.

Abstract: A method and system for decapsulating a multi-chip package is disclosed. The multi-chip package includes a first die and a second die. The first die resides above the second die. The method and system include mechanically removing at least a portion of the first die substantially without destroying the portion of a second die. The method and system also include removing a portion of the multi-chip package between the first die and the second die to expose a portion of the second die substantially without destroying the portion of a second die.

Abstract: An automatic decapsulation system for a device is disclosed. The system comprises an etch plate, an etch head, an acid resistant, high heat endurance and flexible sheet coupled to the etch plate, and a rubber gasket disposed between the sheet and the etch head. The sheet provides a precise etch window and a self-aligning gasket for the device. The rubber gasket creates a tight seal between the device, the sheet, and the etch head. A system in accordance with the present invention utilizes an acid resistant, high heat endurance and flexible sheet in combination with a rubber gasket to seal the device for decapsulation and to provide a well-defined etch window. In addition, the sheet being utilized as the gasket is also utilized as the fixture, thereby eliminating the need to align the gasket to the metal fixture utilized in the conventional system.

Abstract: Aspects for electrical trace inspection during device analysis for devices with solder ball attachments are described. In a method aspect, the method includes forming a desired integrated circuit device including bond wire attachments. The bond wire attachments are then utilized with electrical traces in a transparent tape layer, with visual inspection of the electrical traces performed through the transparent polyimide tape. In an apparatus aspect, the apparatus includes an integrated circuit die, the integrated circuit die including bond pads. The apparatus further includes bond wires coupled to the bond pads of the integrated circuit die, and a transparent tape layer, including a plurality of traces for electrically connecting to the bond wires, wherein visual inspection of the plurality of traces occurs through the transparent tape layer.

Abstract: Aspects for performing decapsulation of multi-chip devices are presented. One aspect includes removing a top die of the multi-chip device without employing a wet chemical etch and removing residual attach and package materials to expose a bottom die of the multi-chip device. An alternate aspect includes utilizing mechanical polishing and wet chemical etching to remove a top die of the multi-chip device, and exposing a bottom die through chemical decapsulation to allow failure analysis of the bottom die. A Flash memory die as a top die and a static random access memory (SRAM) die as a bottom die are included as a multi-chip device capable of decapsulation through these aspects.

Abstract: A system and method for identifying a location of a short in a circuit of a semiconductor device is disclosed. The method and system includes providing a power supply and providing a power distribution network coupled to the power supply. The power distribution network is for distributing power to a portion of the circuit. The power distribution network further including means for selectively disconnecting a portion of the power distribution network. The portion of the power distribution network supplies power to the location of the short.

Abstract: A system and method for detecting a position of a short in a semiconductor device is disclosed. The semiconductor device includes a semiconductor die and a substrate. The method and system include supplying alternating power to the semiconductor device. The method and system further include sensing a plurality of synchronous temperature variations in proximity to a surface of the semiconductor die while power is supplied to the semiconductor die.

Abstract: Aspects for removing device packaging from an FBGA (fine pitch ball grid array) package are described. In an exemplary method aspect, the method includes recessing a predetermined area of the FBGA package, and exposing an integrated circuit die covered by the FBGA package. Device analysis is then performed on the exposed die. The step of recessing further includes milling the predetermined area, while the step of exposing includes chemically etching the FBGA package.