Abstract: A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system.

Abstract: A system and methods for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized. The system may be at least a portion of a computer aided design (CAD) system.

Abstract: A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized.

Abstract: A method and system for metastability verification of an integrated circuit design are provided. An IC design is received and the source-to-destination paths of the IC design are determined. For each of the determined source-to-destination paths, it is determined whether the corresponding source is synchronized. For each source its respective synchronized or unsynchronized result is stored and a report is generated for each source describing whether it is synchronized or unsynchronized.

Abstract: Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.

Abstract: Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.

Abstract: Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.

Abstract: Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.