Patents by Inventor Mohammad Navabi

Mohammad Navabi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113116
    Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for integrated circuit structures that include self-aligned metal gates, self-aligned epitaxial structure, self-aligned terminal contacts over the epitaxial structure, and removal of poly material around a gate during integrated circuit structure manufacture, using a tub gate architecture. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Dan S. LAVRIC, YenTing CHIU, Tahir GHANI, Leonard P. GULER, Mohammad HASAN, Aryan NAVABI-SHIRAZI, Anand S. MURTHY, Wonil CHUNG, Allen B. GARDINER
  • Publication number: 20240105774
    Abstract: Integrated circuit structures having uniform epitaxial source or drain cut are described. For example, an integrated circuit structure includes a first sub-fin structure beneath a first stack of nanowires. A second sub-fin structure is beneath a second stack of nanowires. A first epitaxial source or drain structure is at an end of the first stack of nanowires, the first epitaxial source or drain structure having a first lateral sidewall having a flat vertical surface, and having a second lateral sidewall opposite the first lateral sidewall. A second epitaxial source or drain structure is at an end of the second stack of nanowires, the second epitaxial source or drain structure having a first lateral sidewall having a flat vertical surface, and having a second lateral sidewall opposite the first lateral sidewall, the first lateral sidewall of the second epitaxial source or drain structure laterally spaced apart from the second lateral sidewall of the first epitaxial source or drain structure.
    Type: Application
    Filed: September 28, 2022
    Publication date: March 28, 2024
    Inventors: Leonard P. GULER, Mohammad HASAN, Aryan NAVABI-SHIRAZI, Jessica PANELLA, Saurabh ACHARYA, Desalegne B. TEWELDEBRHAN, Madeleine BEASLEY
  • Patent number: 6559692
    Abstract: A multi-path unity gain buffer circuit and method are implemented in a slew amplifier. The multi-path unity buffer has a high frequency signal path and a low frequency signal path. The high frequency signal path has a differential amplifier powered for providing a high frequency, low accuracy buffering operation. The low frequency signal path is coupled to the high frequency signal path. The low frequency signal path has an operational amplifier powered to provide a low frequency, high bandwidth buffering operation. An output of the operational amplifier is fed back to an input of the operational amplifier through a current varying element that varies current levels of the input of the operational amplifier to remove a level shift of an output signal of the differential amplifier.
    Type: Grant
    Filed: April 23, 1999
    Date of Patent: May 6, 2003
    Assignee: Cirrus Logic, Inc.
    Inventors: Eric Kimball, Perry Heedley, Baker Scott, Eric Smith, Stephen Hodapp, Sumant Ranganathan, Mohammad Navabi
  • Publication number: 20020060587
    Abstract: An output driver (121) for a 10BaseT/100BaseTX transceiver provides a drive capability for either a 10BaseT output or a 100BaseTX output. The driver includes a voltage-to-current converter for converting the voltage to a current level which is then selectably switched to the input of two constant output impedance buffers (327) and (328). For the 100BaseTX mode, a constant current is provided to the buffers and then the current switched in a multi-level mode in accordance with an MLT-3 encoding scheme with a current switch (311). The buffers (327) and (328) are trimmed as a function of temperature by varying the current generated by the voltage-to-current converter (303). This trimming is facilitated by generating an internal current with the voltage-to-current converter (303) and then summing therewith a zero temperature coefficient current referenced to an external resistor.
    Type: Application
    Filed: April 23, 1999
    Publication date: May 23, 2002
    Inventors: ERIC KIMBALL, PERRY HEEDLEY, BAKER SCOTT, ERIC SMITH, STEPHEN HODAPP, SUMANT RANGANATHAN, MOHAMMAD NAVABI