Abstract: Apparatus and methods may include a method for validating a script. The script may be a script for firing a job in an Autosys™ application deployed in a predetermined environment. The validating may use a validation system. The method may include providing a plurality of pre-deployment validation utility actions. The plurality of pre-deployment utility actions may include permitting only insert (INS), update (UPD) and delete (DEL) as actions in the script. The permitting may use an action name review utility. The plurality of pre-deployment utility actions may include permitting only command (CMD) or box parameter types (BMT) in the script. The permitting may use a parameter type review utility. The plurality of pre-deployment utility actions may include specifying only NULL, FDR and LMCTR as project codes. The specifying may use a project code specifier utility.

Abstract: Apparatus and methods may include a method for enabling customized jobs deployment in Autosys™, reviewing of execution results of the jobs in Autosys™, and querying the execution results. The method may include providing a verification of the deployment of a plurality of job scripts in a staging area. The staging area may be configured for arranging and deploying a plurality of job scripts in Autosys™. The method may include visually indicating, in a status line, whether each of the plurality of job scripts has been deployed in Autosys™ or is set to be deployed to, and executed in, Autosys™. The method may include importing selected contents of a log folder from Autosys™. The importing may use an import utility.

Abstract: Apparatus and methods may include methods for enabling customized jobs deployment in Autosys™. The method may include staging, in a staging area set forth in a visible display, a job script for deployment in Autosys™. The method may include providing a verification of the deployment of the job script in Autosys™. The method may include visually indicating, on a status line, whether the job script has been deployed in Autosys™ or is set to be deployed to, and executed in, Autosys™. The method may include, following an attempt to deploy from the staging area, displaying either a complete job execution of the job script in Autosys™ of the deployed job or a failed job execution of the job script in Autosys™ of the deployed job.

Abstract: Apparatus and methods may include a method for using a single script framework to generate a plurality of JIL files. Each of the plurality of JIL files may be for use in one of a plurality of multiple environments. The methods may include providing, based on the jobs information, the jobs attribute values and the SQL content, parameters to create a job, update a job and/or delete a job. The providing may use an AutoSys™ jobs table. The AutoSys™ jobs table may include jobs information, jobs attribute values, and Sequel (SQL) content to be run.

Abstract: Apparatus and methods may include a method for enabling customized jobs deployment in Autosys TM, reviewing of deployment results of said jobs in Autosys TM, and querying said deployment results. The method may include providing a verification of the deployment in a staging area. The staging area may be configured for arranging and deploying a plurality of job scripts in Autosys TM. Each job script may be interrelated with one or more other job scripts. The method may include visually indicating, in a status line, whether the job script has been deployed in Autosys TM or is set to be deployed to Autosys TM. The method may include further visually indicating in what way the job script is interrelated with one or more other job scripts. The method may include importing selected contents of a log folder from Autosys TM.

Abstract: Apparatus and methods may include a method for enabling customized jobs deployment in Autosys TM, reviewing of deployment results of said jobs in Autosys TM, and querying said deployment results. The method may include providing a verification of the deployment in a staging area. The staging area may be configured for arranging and deploying a plurality of job scripts in Autosys TM. Each job script may be interrelated with one or more other job scripts. The method may include visually indicating, in a status line, whether the job script has been deployed in Autosys TM or is set to be deployed to Autosys TM. The method may include further visually indicating in what way the job script is interrelated with one or more other job scripts. The method may include importing selected contents of a log folder from Autosys TM.

Abstract: Apparatus and methods may include a method for enabling customized jobs deployment in Autosys™, reviewing of execution results of the jobs in Autosys™, and querying the execution results. The method may include providing a verification of the deployment of a plurality of job scripts in a staging area. The staging area may be configured for arranging and deploying a plurality of job scripts in Autosys™. The method may include visually indicating, in a status line, whether each of the plurality of job scripts has been deployed in Autosys™ or is set to be deployed to, and executed in, Autosys™. The method may include importing selected contents of a log folder from Autosys™. The importing may use an import utility.

Abstract: Apparatus and methods may include a method for validating a script. The script may be a script for firing a job in an Autosys TM application deployed in a predetermined environment. The validating may use a validation system. The method may include providing a plurality of pre-deployment validation utility actions. The plurality of pre-deployment utility actions may include permitting only insert (INS), update (UPD) and delete (DEL) as actions in the script. The permitting may use an action name review utility. The plurality of pre-deployment utility actions may include permitting only command (CMD) or box parameter types (BMT) in the script. The permitting may use a parameter type review utility. The plurality of pre-deployment utility actions may include specifying only NULL, FDR and LMCTR as project codes. The specifying may use a project code specifier utility.

Abstract: Apparatus and methods may include a method for using a single script framework to generate a plurality of JIL files. Each of the plurality of JIL files may be for use in one of a plurality of multiple environments. The methods may include providing, based on the jobs information, the jobs attribute values and the SQL content, parameters to create a job, update a job and/or delete a job. The providing may use an AutoSys™ jobs table. The AutoSys™ jobs table may include jobs information, jobs attribute values, and Sequel (SQL) content to be run.

Abstract: Apparatus and methods may include methods for enabling customized jobs deployment in Autosys™. The method may include staging, in a staging area set forth in a visible display, a job script for deployment in Autosys™. The method may include providing a verification of the deployment of the job script in Autosys™. The method may include visually indicating, on a status line, whether the job script has been deployed in Autosys™ or is set to be deployed to, and executed in, Autosys™. The method may include, following an attempt to deploy from the staging area, displaying either a complete job execution of the job script in Autosys™ of the deployed job or a failed job execution of the job script in Autosys™ of the deployed job.

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: A bit stream multiplexer and a bit stream demultiplexer of the present invention couples a communication Application Specific Integrate Circuit (ASIC) to a high-speed bit stream media. The bit stream multiplexer includes a first transmit data multiplexing integrated circuit having an input that receives a first plurality of bit streams at a first bit rate from the communication ASIC and an output that produces a second plurality of bit streams at a second bit rate, the second plurality having fewer bit streams than said first plurality. It further includes a second transmit data multiplexing integrated circuit having an input that receives the second plurality of bit streams at the second bit rate and an output that produces a single bit stream at a line bit rate, the single bit stream having a predetermined bit order. The bit stream demultiplexer includes similar demultiplexing integrated circuits.

Abstract: A multiple bit stream interface interfaces a first transmit data multiplexing integrated circuit and a second transmit data multiplexing integrated circuit. The multiple bit stream interface includes an interface plurality of transmit bit streams each of which carries a respective bit stream at an interface bit rate. The interface further includes a transmit data clock operating at a frequency corresponding to one-half of the interface bit rate. The first transmit data multiplexing integrated circuit receives a first plurality of transmit bit streams from a communication ASIC at a first bit rate. The second transmit data multiplexing integrated circuit produces a single bit stream output at a line bit rate. The interface plurality of transmit bit streams is divided into a first group and a second group, wherein the first group is carried on first group of lines and the second group is carried on a second group of lines.

Abstract: A multi-stage bit stream multiplexer that divides multiplexing functions between two or more integrated circuits. The first integrated circuit receives 16 bit streams to produce 4 output bits streams with a nominal data rate of 10 GBPS. A second integrated circuit multiplexes the 4 streams and to a bit stream with a data rate of 40 GBPS. The first IC is made in a standard CMOS process while the second IC is made using processes that support higher switching rates. The first IC produces a source-centered double data rate forward transmit clock from a reference clock selectable from either a crystal oscillator, a voltage controlled oscillator using a loop clock from the receive side of the bit stream multiplexer or a reverse clock generated by the second IC. The reverse clock can be selected as the source of the reference either by default, or in response to a specific condition.

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract: A bit stream demultiplexer that couples a high-speed bit stream media to a communication Application Specific Integrated Circuit (ASIC). The bit stream multiplexer performs its demultiplexing function staged within at least two integrated circuits. The first Integrated Circuit (IC) receives a first bit stream and performs a first demultiplexing function. A second IC performs a second demultiplexing function. The second IC acts as either a slave or a master to the first IC. In a slave mode, the second IC depends upon a transmit data clock from the first IC for latching bit stream data received from the first IC. When the second IC operates in the master mode, the second IC uses the transmit data clock from first IC as a reference input for a PLL to generate a Receive Data Clock. If an LOL or LOS occurs within the first IC, a signal to the second IC indicates these conditions causing the second IC to switch to a local oscillator reference clock to generate the Receive Data Clock.