Patents by Inventor Mohammad Nizam Kabir
Mohammad Nizam Kabir has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11689100Abstract: Aspects of the subject disclosure may include, for example, obtaining, by a first circuit of a charge pump circuit, charge sourced from a power supply operative at a first voltage level, wherein the first circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors is rated for operation at an applied voltage that is less than the first voltage level, storing the charge in a first capacitor of the first circuit at a first point in time, and transferring the charge stored in the first capacitor to a second capacitor of a second circuit of the charge pump circuit at a second point in time such that the second capacitor stores the charge, wherein the second point in time is subsequent to the first point in time. Other embodiments are disclosed.Type: GrantFiled: July 15, 2021Date of Patent: June 27, 2023Assignee: NXP USA, Inc.Inventors: Mohammad Nizam Kabir, Madan Mohan Reddy Vemula, Xu Jason Ma
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Publication number: 20230015111Abstract: Aspects of the subject disclosure may include, for example, obtaining, by a first circuit of a charge pump circuit, charge sourced from a power supply operative at a first voltage level, wherein the first circuit comprises a first plurality of transistors, and wherein each of the first plurality of transistors is rated for operation at an applied voltage that is less than the first voltage level, storing the charge in a first capacitor of the first circuit at a first point in time, and transferring the charge stored in the first capacitor to a second capacitor of a second circuit of the charge pump circuit at a second point in time such that the second capacitor stores the charge, wherein the second point in time is subsequent to the first point in time. Other embodiments are disclosed.Type: ApplicationFiled: July 15, 2021Publication date: January 19, 2023Applicant: NXP USA, Inc.Inventors: Mohammad Nizam Kabir, Madan Mohan Reddy Vemula, Xu Jason Ma
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Patent number: 11422578Abstract: A low dropout regulator includes a first stage that generate a first output voltage and a second stage that generates a second output voltage different from the first output voltage. The first stage and the second stage are coupled in parallel to a node, the stages are selectively controlled respective first and second output signals based on different conditions. One condition may be operation of a load in one or more predetermined modes. Another condition may be transition between modes. Selective control of the first stage during a mode transition may reduce voltage undershoot or voltage overshoot in the load.Type: GrantFiled: April 28, 2020Date of Patent: August 23, 2022Assignee: NXP B.V.Inventors: Xiaoqun Liu, Madan Mohan Reddy Vemula, Mohammad Nizam Kabir
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Publication number: 20210333812Abstract: A low dropout regulator includes a first stage that generate a first output voltage and a second stage that generates a second output voltage different from the first output voltage. The first stage and the second stage are coupled in parallel to a node, the stages are selectively controlled respective first and second output signals based on different conditions. One condition may be operation of a load in one or more predetermined modes. Another condition may be transition between modes. Selective control of the first stage during a mode transition may reduce voltage undershoot or voltage overshoot in the load.Type: ApplicationFiled: April 28, 2020Publication date: October 28, 2021Inventors: Xiaoqun LIU, Madan Mohan Reddy VEMULA, Mohammad Nizam KABIR
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Patent number: 10211820Abstract: Embodiments of a multi-stage clock generator architecture that generates multiple non-overlapping clock phase signals includes: a first stage clock generator configured to: divide an input clock signal into a number of clock signals, synchronize each clock signal to a transition edge of a synchronization signal to produce synchronized clock signals, wherein the synchronization signal is a delayed version of the input clock signal by at least an amount sufficient to ensure that each of the clock signals become stable in response to a transition edge of the input clock signal, and generate a number of clock phase signals based on the synchronized clock signals. The architecture also includes a later stage clock generator configured to: generate a set of mutually non-overlapping clock phase signals based on the input clock signal.Type: GrantFiled: November 29, 2016Date of Patent: February 19, 2019Assignee: NXP USA, Inc.Inventors: Mohammad Nizam Kabir, Mariam Hoseini, Rakesh Shiwale, Doug Garrity
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Patent number: 9991900Abstract: A digital to analog converter convert digital data in binary format to thermometer bit vectors. A first set of the thermometer bit vectors corresponds to most significant bits of the digital data and a second set of the thermometer bit vectors corresponds to least significant bits of the digital data. Connections of first current sources corresponding to the first set of the thermometer bit vectors and second current sources corresponding to the second set of the thermometer bit vectors are dynamically and randomly alternated to a first output line and a second output line. Calibration current is applied to the second current sources so a total current of the second current sources and the calibration current is within a predetermined range of an average current of the first current sources.Type: GrantFiled: August 2, 2017Date of Patent: June 5, 2018Assignee: NXP USA, Inc.Inventors: Mohammad Nizam Kabir, Mariam Hoseini, Brandt Braswell
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Publication number: 20180152181Abstract: Embodiments of a multi-stage clock generator architecture that generates multiple non-overlapping clock phase signals includes: a first stage clock generator configured to: divide an input clock signal into a number of clock signals, synchronize each clock signal to a transition edge of a synchronization signal to produce synchronized clock signals, wherein the synchronization signal is a delayed version of the input clock signal by at least an amount sufficient to ensure that each of the clock signals become stable in response to a transition edge of the input clock signal, and generate a number of clock phase signals based on the synchronized clock signals. The architecture also includes a later stage clock generator configured to: generate a set of mutually non-overlapping clock phase signals based on the input clock signal.Type: ApplicationFiled: November 29, 2016Publication date: May 31, 2018Inventors: Mohammad Nizam KABIR, Mariam HOSEINI, Rakesh SHIWALE, Doug GARRITY
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Patent number: 9748964Abstract: Embodiments of a multi-channel analog to digital converter (ADC) include: a first multiplying digital to analog converter (MDAC) having: first and second switched capacitor circuit paths respectively coupled between first and second input nodes and an input node of a first gain element, a second MDAC having: third and fourth switched capacitor circuit paths respectively coupled between third and fourth input nodes and an input node of a second gain element, a third MDAC having: fifth and sixth switched capacitor circuit paths respectively coupled between a fifth input node and an input node of a third gain element, seventh and eighth switched capacitor circuit paths respectively coupled between a sixth input node and the input node of the third gain element, the fifth input node coupled to an output node of the first gain element, the sixth input node coupled to an output node of the second gain element.Type: GrantFiled: November 29, 2016Date of Patent: August 29, 2017Assignee: NXP USA, Inc.Inventors: Mohammad Nizam Kabir, Doug Garrity, Mariam Hoseini, Rakesh Shiwale
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Patent number: 9548757Abstract: A digital to analog converter including a current source for providing a master current, a first sub digital to analog converter coupled to the current source which generates a plurality of currents, and a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter which generates a second plurality of currents. The digital to analog converter also includes an overlap adjustment circuit coupled with the second sub digital to analog converter which adds current. The digital to analog converter is configured to operate in a first mode for generating a sine wave with a first bit level accuracy and, when in the first mode, the overlap adjustment circuit adds no current.Type: GrantFiled: January 8, 2016Date of Patent: January 17, 2017Assignee: NXP USA, Inc.Inventors: Mohammad Nizam Kabir, Brandt Braswell, Mariam Hoseini
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Publication number: 20160269041Abstract: A digital to analog converter including a current source for providing a master current, a first sub digital to analog converter coupled to the current source which generates a plurality of currents, and a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter which generates a second plurality of currents. The digital to analog converter also includes an overlap adjustment circuit coupled with the second sub digital to analog converter which adds current. The digital to analog converter is configured to operate in a first mode for generating a sine wave with a first bit level accuracy and, when in the first mode, the overlap adjustment circuit adds no current.Type: ApplicationFiled: January 8, 2016Publication date: September 15, 2016Inventors: Mohammad Nizam KABIR, Brandt BRASWELL, Mariam HOSEINI
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Patent number: 9264062Abstract: A digital to analog converter including a current source for providing a master current, a first sub digital to analog converter coupled to the current source which generates a plurality of currents, and a second sub digital to analog converter coupled to at least one of the plurality of currents from the first sub digital to analog converter which generates a second plurality of currents. The digital to analog converter also includes an overlap adjustment circuit coupled with the second sub digital to analog converter which adds current. The digital to analog converter is configured to operate in a first mode for generating a sine wave with a first bit level accuracy and, when in the first mode, the overlap adjustment circuit adds no current.Type: GrantFiled: March 11, 2015Date of Patent: February 16, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Mohammad Nizam Kabir, Brandt Braswell, Mariam Hoseini
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Patent number: 9252797Abstract: The embodiments described herein provide a digital-to-analog converter (DAC). The DAC implements a stepped return-to-zero (RZ) pulse scheme, where the DAC output includes the superposition of multiple time-offset RZ pulses. In one embodiment, the DAC includes a first switching element, a second switching element, a current source, and a current sink. The first switching element generates first RZ pulses, and the second switching element generates second RZ pulses, where the second RZ pulses are time-offset from the first RZ pulses. The first RZ pulses and second RZ pulses are combined to provide stepped RZ pulse output signal.Type: GrantFiled: October 31, 2014Date of Patent: February 2, 2016Assignee: FREESCALE SEMICONDUCTOR INC.Inventors: Mohammad Nizam Kabir, Mariam Hoseini, Brandt Braswell, Bruce M. Newman
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Patent number: 9148169Abstract: A quantizer for an analog to digital converter has an input for receiving an analog input signal. A detector senses a common mode voltage component of the input signal. A reference voltage source produces a plurality of reference voltages. A voltage source biases the reference voltage source in response to the sensed common mode voltage component. Therefore, the common mode voltage in the input signal establishes the common mode voltage of the reference voltage source. A plurality of comparators are connected to the reference voltage source, wherein each of the plurality of comparators compares the input signal to one of the plurality of reference voltages and produces a output bit denoting a result of the comparing.Type: GrantFiled: February 25, 2014Date of Patent: September 29, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Mohammad Nizam Kabir, Brandt Braswell, Mariam Hoseini
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Publication number: 20150244393Abstract: A quantizer for an analog to digital converter has an input for receiving an analog input signal. A detector senses a common mode voltage component of the input signal. A reference voltage source produces a plurality of reference voltages. A voltage source biases the reference voltage source in response to the sensed common mode voltage component. Therefore, the common mode voltage in the input signal establishes the common mode voltage of the reference voltage source. A plurality of comparators are connected to the reference voltage source, wherein each of the plurality of comparators compares the input signal to one of the plurality of reference voltages and produces a output bit denoting a result of the comparing.Type: ApplicationFiled: February 25, 2014Publication date: August 27, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Mohammad Nizam Kabir, Brandt Braswell, Mariam Hoseini
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Patent number: 8836566Abstract: A quantizer includes a voltage reference network and a set of comparators coupled with the voltage reference network. The voltage reference network generates a plurality of reference voltages. Each of the comparators receives an input signal and produces a sequence of digital samples. The set of comparators includes first, second, and third subsets of comparators. Each comparator of the first subset includes a switched capacitor stage, each comparator of the second subset includes a preamplifier stage, and each comparator of the third subset includes a switched capacitor stage. The first and third subsets of comparators compares the input signal with reference voltages corresponding to the upper and lower voltage ranges of the input signal, and the second subset of comparators compares the input signal with reference voltages corresponding to the middle voltage range of the input signal.Type: GrantFiled: February 21, 2013Date of Patent: September 16, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Mohammad Nizam Kabir, Brandt Braswell, Rakesh Shiwale
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Publication number: 20140232579Abstract: A quantizer includes a voltage reference network and a set of comparators coupled with the voltage reference network. The voltage reference network generates a plurality of reference voltages. Each of the comparators receives an input signal and produces a sequence of digital samples. The set of comparators includes first, second, and third subsets of comparators. Each comparator of the first subset includes a switched capacitor stage, each comparator of the second subset includes a preamplifier stage, and each comparator of the third subset includes a switched capacitor stage. The first and third subsets of comparators compares the input signal with reference voltages corresponding to the upper and lower voltage ranges of the input signal, and the second subset of comparators compares the input signal with reference voltages corresponding to the middle voltage range of the input signal.Type: ApplicationFiled: February 21, 2013Publication date: August 21, 2014Inventors: Mohammad Nizam Kabir, Brandt Braswell, Rakesh Shiwale
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Patent number: 7649957Abstract: A multi-stage non-overlapping clock signal generator as described herein is suitable for use with a pipelined analog-to-digital converter architecture. The clock signal generator generally includes a back end clock generator, a second stage clock generator, and a first stage clock generator coupled in series. The clock signal generator may also include any number of intermediate stage clock generators coupled in series between the back end clock generator and the second stage clock generator. Example implementations of the various clock generator stages are also described herein.Type: GrantFiled: March 22, 2006Date of Patent: January 19, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Douglas A. Garrity, Mohammad Nizam Kabir