Abstract: An apparatus for providing multi-cell support in a telecommunications network is described. The apparatus includes a modem board and a multi-core processor having a plurality of processor cores attached to the modem board. A single partition is defined with all of the processor cores included in it. The single partition is used to execute all control plane functions and all data plane functions. Typically, the multi-core processor is configured to include a core abstraction layer that hides any core specific details from application software running on the processor cores in the single partition and to serve at least three cells in the telecommunications network, each cell having a corresponding uplink scheduler and a corresponding downlink scheduler. In this configuration there is no need to use a hypervisor, since there is only one OS instance running (a potential cost saving).

Abstract: A buffer management mechanism in a multi-core processor for use on a modem in a telecommunications network is described herein. The buffer management mechanism includes a buffer module that provides buffer management services for one or more Layer 2 applications, wherein the buffer module at least provides a user space application interface to application software running in user space. The buffer management mechanism also includes a buffer manager that manages a plurality of separate pools of tokens, wherein the tokens comprise pointers to memory areas in external memory. In addition, the buffer management mechanism includes a custom driver that manages Data Path Acceleration Architecture (DPAA) resources including buffer pools and frame queues to be used for user plane data distributing.

Abstract: A method and system for dynamic power control for next generation LTE base stations are described herein. More particularly, a dynamic power control management process may run, for example, in an OA&M module on the control plane core of the base station. The dynamic power control management process collaborates with various components, such as a call management processing module and a transport process module, to periodically obtain information regarding the number of active calls as well as the uplink and downlink data rates for a given interval for a particular cell. The dynamic power control management process polls the call management processing module and transport process module periodically according to a tunable parameter for the key values. Based on this information, the dynamic power control management process determines whether a particular cell on the base station is running below a threshold at which dynamic power control could be triggered.

Abstract: A system for providing multi-cell support within a single SMP partition in a telecommunications network is disclosed. The typically includes a modem board and a multi-core processor having a plurality of processor cores, wherein the multi-core processor is configured to disable non-essential interrupts arriving on a plurality of data plane cores and route the non-essential interrupts to a plurality of control plane cores. Optionally, the multi-core processor may be configured so that all non-real-time threads and processes are bound to processor cores that are dedicated for all control plane activities and processor cores that are dedicated for all data plane activities will not host or run any threads that are not directly needed for data path implementation or Layer 2 processing.

Abstract: A method and system that helps to ensure that any cell crash (i.e., an involuntarily action occurring as a result of a software bug or malfunction) is localized to a single cell on a single modem board that supports multi-cell configuration. In this regard, the control plane and the remaining cells that are configured on the modem board should remain operational. Further the operator should be able to choose to take corrective action (i.e., reboot, reconfigure, delete, or create) with regard to a cell on the modem board without impacting the operations of the other configured cells.

Abstract: A computer-implemented system and method for a lock-less, zero data copy messaging mechanism in a multi-core processor for use on a modem in a telecommunications network are described herein. The method includes, for each of a plurality of processing cores, acquiring a kernel to user-space (K-U) mapped buffer and corresponding buffer descriptor, inserting a data packet into the buffer; and inserting the buffer descriptor into a circular buffer. The method further includes creating a frame descriptor containing the K-U mapped buffer pointer, inserting the frame descriptor onto a frame queue specified by a dynamic PCD rule mapping IP addresses to frame queues, and creating a buffer descriptor from the frame descriptor.

Abstract: A buffer management mechanism in a multi-core processor for use on a modem in a telecommunications network is described herein. The buffer management mechanism includes a buffer module that provides buffer management services for one or more Layer 2 applications, wherein the buffer module at least provides a user space application interface to application software running in user space. The buffer management mechanism also includes a buffer manager that manages a plurality of separate pools of tokens, wherein the tokens comprise pointers to memory areas in external memory. In addition, the buffer management mechanism includes a custom driver that manages Data Path Acceleration Architecture (DPAA) resources including buffer pools and frame queues to be used for user plane data distributing.

Abstract: A new sub-system, the core abstraction layer (CAL), is introduced to the middleware layer of the multi-core processor based modem board. This new module provides an abstraction for the multi-core FSL P4080 processor and its DPAA. For the deployment of this modem board, the CAL will provide various services such as zero copy lock free buffer management scheme to LTE L2 application, and the support for the new backplane Ethernet driver (BED) interface for the RLC SDU transmission and reception to and from the controller board for multi-cell configuration.

Abstract: An apparatus for providing multi-cell support in a telecommunications network is described. The apparatus includes a modem board and a multi-core processor having a plurality of processor cores attached to the modem board. A single partition is defined with all of the processor cores included in it. The single partition is used to execute all control plane functions and all data plane functions. Typically, the multi-core processor is configured to include a core abstraction layer that hides any core specific details from application software running on the processor cores in the single partition and to serve at least three cells in the telecommunications network, each cell having a corresponding uplink scheduler and a corresponding downlink scheduler. In this configuration there is no need to use a hypervisor, since there is only one OS instance running (a potential cost saving).