Patents by Inventor Mohammad R. Mirabedini

Mohammad R. Mirabedini has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8021955
    Abstract: Provided are methods and composition for forming a multi-layer isolation structure on an integrated circuit substrate. A process can include selecting a lower dielectric material for the lower dielectric layer and selecting an upper dielectric material for the upper dielectric layer. A range of effective dielectric constants that correspond to the thicknesses the lower and upper dielectric materials are selected. A range of thicknesses for each of the lower and upper dielectric layers are determined from a range of acceptable dielectric constants using information indicating an effective dielectric constant corresponding to thicknesses of the materials for both the lower upper dielectric layers, enabling the formation of the multi-layer isolation structure.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: September 20, 2011
    Assignee: LSI Logic Corporation
    Inventors: Venkatesh P. Gopinath, Arvind Kamath, Mohammad R. Mirabedini, Ming-Yi Lee
  • Patent number: 7619294
    Abstract: Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: November 17, 2009
    Assignee: LSI Corporation
    Inventors: Venkatesh P. Gopinath, Arvind Kamath, Mohammad R. Mirabedini, Ming-Yi Lee
  • Patent number: 7429749
    Abstract: An integrated circuit (IC) includes a strained-silicon layer formed by deposition of amorphous silicon onto either a region of a semiconductor layer that has been implanted with ions to create a larger spacing between atoms in a crystalline lattice of the semiconductor layer or a silicon-ion layer that has been epitaxially grown on the semiconductor layer to have an increased spacing between atoms in the silicon-ion layer. Alternatively, the IC includes a strained-silicon layer formed by silicon epitaxial growth onto the region of the semiconductor layer that has been implanted with ions. The IC also preferably includes a CMOS device that preferably, but not necessarily, incorporates sub-0.1 micron technology. The implanted ions may preferably be heavy ions, such as germanium ions, antimony ions or others. Ion implantation may be done with a single implantation process, as well as with multiple implantation processes.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: September 30, 2008
    Assignee: LSI Corporation
    Inventors: Agajan Suvkhanov, Mohammad R. Mirabedini
  • Patent number: 7408227
    Abstract: An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric may be a crystalline carbon or carbon-containing film.
    Type: Grant
    Filed: September 20, 2006
    Date of Patent: August 5, 2008
    Assignee: LSI Corporation
    Inventors: Mohammad R. Mirabedini, Valeriy Sukharev
  • Patent number: 7138292
    Abstract: An integrated circuit, or portion thereof, such as a CMOS device, includes an epitaxially grown dielectric on a silicon carbide base. The epitaxially grown dielectric forms a gate dielectric and the silicon carbide base serves as a channel region for the CMOS device. In various embodiments, the epitaxially grown dielectric may be a crystalline carbon or carbon-containing film.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: November 21, 2006
    Assignee: LSI Logic Corporation
    Inventors: Mohammad R. Mirabedini, Valeriy Sukharev
  • Patent number: 7129516
    Abstract: An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. A strained-silicon layer is preferably, but not necessarily, formed above the ion-implanted layer of the semiconductor substrate. The strained-silicon layer may be formed by a silicon epitaxial growth on the ion-implanted layer or by causing the ions to recoil into the semiconductor substrate with such energy that a region of the semiconductor substrate in the vicinity of the surface thereof is left substantially free of the ions, thereby forming a strained-silicon layer in the substantially ion-free region.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: October 31, 2006
    Assignee: LSI Logic Corporation
    Inventors: Agajan Suvkhanov, Mohammad R. Mirabedini
  • Patent number: 7001823
    Abstract: Provided are methods and composition for forming an isolation structure on an integrated circuit substrate. First, a trench is etched in the integrated circuit substrate. A lower dielectric layer is then formed in the trench such that the lower dielectric layer at least partially fills the trench. An upper dielectric layer is then formed over the lower dielectric layer to create an isolation structure, the upper dielectric layer and the lower dielectric layer together having an effective dielectric constant that is less than that of silicon dioxide, thereby enabling capacitance associated with the isolation structure to be reduced.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: February 21, 2006
    Assignee: LSI Logic Corporation
    Inventors: Venkatesh P. Gopinath, Arvind Kamath, Mohammad R. Mirabedini, Ming-Yi Lee
  • Patent number: 6989331
    Abstract: A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: January 24, 2006
    Assignee: LSI Logic Corporation
    Inventors: Venkatesh Gopinath, Arvind Kamath, Mohammad R. Mirabedini, Ming-Yi Lee, Brian A. Baylis
  • Patent number: 6982229
    Abstract: An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. A strained-silicon layer is preferably, but not necessarily, formed above the ion-implanted layer of the semiconductor substrate. The strained-silicon layer may be formed by a silicon epitaxial growth on the ion-implanted layer or by causing the ions to recoil into the semiconductor substrate with such energy that a region of the semiconductor substrate in the vicinity of the surface thereof is left substantially free of the ions, thereby forming a strained-silicon layer in the substantially ion-free region.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: January 3, 2006
    Assignee: LSI Logic Corporation
    Inventors: Agajan Suvkhanov, Mohammad R. Mirabedini
  • Patent number: 6930362
    Abstract: A calcium doped polysilicon gate electrodes for PMOS containing semiconductor devices. The calcium doped PMOS gate electrodes reduce migration of the boron dopant out of the gate electrode, through the gate dielectric and into the substrate thereby reducing the boron penetration problem increasingly encountered with smaller device size regimes and their thinner gate dielectrics. Calcium doping of the gate electrode may be achieved by a variety of techniques. It is further believed that the calcium doping may improve the boron dopant activation in the gate electrode, thereby further improving performance.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: August 16, 2005
    Assignee: LSI Logic Corporation
    Inventors: Mohammad R. Mirabedini, Grace S. Sun, Sheldon Aronowitz
  • Publication number: 20040247894
    Abstract: An integrated circuit (IC) includes a strained-silicon layer formed by deposition of amorphous silicon onto either a region of a semiconductor layer that has been implanted with ions to create a larger spacing between atoms in a crystalline lattice of the semiconductor layer or a silicon-ion layer that has been epitaxially grown on the semiconductor layer to have an increased spacing between atoms in the silicon-ion layer. Alternatively, the IC includes a strained-silicon layer formed by silicon epitaxial growth onto the region of the semiconductor layer that has been implanted with ions. The IC also preferably includes a CMOS device that preferably, but not necessarily, incorporates sub-0.1 micron technology. The implanted ions may preferably be heavy ions, such as germanium ions, antimony ions or others. Ion implantation may be done with a single implantation process, as well as with multiple implantation processes.
    Type: Application
    Filed: June 4, 2003
    Publication date: December 9, 2004
    Inventors: Agajan Suvkhanov, Mohammad R. Mirabedini
  • Publication number: 20040206951
    Abstract: An integrated circuit (IC) includes a CMOS device with a channel region that has ions implanted therein. The IC preferably incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. The ion-implanted channel region preferably has a carrier mobility that is greater than that for a region that is not implanted with the ions.
    Type: Application
    Filed: April 18, 2003
    Publication date: October 21, 2004
    Inventors: Mohammad R. Mirabedini, Agajan Suvkhanov
  • Publication number: 20040206950
    Abstract: An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. A strained-silicon layer is preferably, but not necessarily, formed above the ion-implanted layer of the semiconductor substrate. The strained-silicon layer may be formed by a silicon epitaxial growth on the ion-implanted layer or by causing the ions to recoil into the semiconductor substrate with such energy that a region of the semiconductor substrate in the vicinity of the surface thereof is left substantially free of the ions, thereby forming a strained-silicon layer in the substantially ion-free region.
    Type: Application
    Filed: April 18, 2003
    Publication date: October 21, 2004
    Inventors: Agajan Suvkhanov, Mohammad R. Mirabedini