Abstract: A subranging analog-to-digital converter wherein, during a first phase, a differential analog input voltage is held by a track and hold circuit and is fed to a low resolution flash ADC to provide the most significant bits (MSBs). During a second or recirculating phase, flash ADC output segments corresponding to the MSBs are fed to respective current switches of a current DAC to produce complementary analog conversion currents that are coupled to the track and hold circuit. In response to the complementary DAC currents, the output stage of the track and hold circuit is used to subtract a voltage corresponding to the MSBs from the input voltage without the use of a separate subtractor. Further, the DAC current switches provide equal currents during the first or MSB phase to deactivate the subtraction function during the first phase.