Abstract: A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.

Abstract: Systems and methods for clock recovery are disclosed. The method comprises generating, by a first dynamic phase interpolator, a first center clock signal, and generating, by a second dynamic phase interpolator, a second center clock signal. The method further comprises outputting, by a static phase interpolator, an edge clock signal based on the first and second center clock signals.

Abstract: A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.

Abstract: Systems and methods for clock recovery are disclosed. The method comprises generating, by a first dynamic phase interpolator, a first center clock signal, and generating, by a second dynamic phase interpolator, a second center clock signal. The method further comprises outputting, by a static phase interpolator, an edge clock signal based on the first and second center clock signals.

Abstract: A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.