Abstract: Provided are methods and systems for preventing hardware Trojan insertion. An example method can comprise determining unused space in an integrated circuit (IC), selecting a plurality of built-in self-authentication (BISA) filler cells based on the determined unused space, and placing the selected plurality of BISA filler cells onto the unused space. The plurality of BISA filler cells can be connected to form a plurality of BISA blocks. The plurality of BISA blocks can correspond to a plurality of signatures. A modification of one or more BISA filler cell can lead to an alteration of one or more signatures.

Abstract: Provided are methods, systems, and devices for preventing hardware piracy.

Abstract: Provided are methods and systems for test power analysis. An example method can comprise creating a test pattern from topology data of an integrated circuit and creating a map from the topology data of the integrated circuit. A test power analysis of the integrated circuit can be performed using the created test pattern and the map. In an aspect, an example method can comprise obtaining transition information via monitoring transitions of a plurality of test cycles in a test session of an integrated circuit. Simulation data can be obtained via simulating a plurality of functions of the plurality of test cycles in the test session of the integrated circuit using the transition information. A test power analysis of the plurality of test cycles in the test session of the integrated circuit can be performed using the obtained simulation data.

Abstract: Provided are methods, systems, and devices for preventing hardware piracy.

Abstract: Aspects of the disclosure relate to combining on-chip structure with external current measurements for threat detection in an integrated circuit. This method considers Trojans' impact on neighboring cells and on the entire IC's power consumption, and effectively localizes the measurement of dynamic power. An on-chip structure can permit threat detections. In one aspect, the on-chip structure can comprise a plurality of sensors distributed across the entirety of the IC, with each sensor of the plurality of sensors being placed in different rows of a standard-cell design. In another aspect, data analysis can permit separating effect of process variations on transient power usage of the IC from effects of a hardware threat such power usage. The on-chip structure also can be employed for implementation of a PE-PUF.

Abstract: Provided are methods and systems for preventing hardware Trojan insertion. An example method can comprise determining unused space in an integrated circuit (IC), selecting a plurality of built-in self-authentication (BISA) filler cells based on the determined unused space, and placing the selected plurality of BISA filler cells onto the unused space. The plurality of BISA filler cells can be connected to form a plurality of BISA blocks. The plurality of BISA blocks can correspond to a plurality of signatures. A modification of one or more BISA filler cell can lead to an alteration of one or more signatures.

Abstract: An apparatus for detection of integrated circuit recovery is disclosed. An example apparatus can comprise a first sensor embedded in an integrated circuit. The example apparatus can comprise a second sensor embedded in the integrated circuit. The example apparatus can comprise a selector unit configured to select one of the first sensor or the second sensor. The example apparatus can also comprise a monitor unit configured to receive output signal from the first sensor and the second sensor and to supply the output signal to an analysis unit.

Abstract: Aspects of the disclosure relate to combining on-chip structure with external current measurements for threat detection in an integrated circuit. This method considers Trojans' impact on neighboring cells and on the entire IC's power consumption, and effectively localizes the measurement of dynamic power. An on-chip structure can permit threat detections. In one aspect, the on-chip structure can comprise a plurality of sensors distributed across the entirety of the IC, with each sensor of the plurality of sensors being placed in different rows of a standard-cell design. In another aspect, data analysis can permit separating effect of process variations on transient power usage of the IC from effects of a hardware threat such power usage. The on-chip structure also can be employed for implementation of a PE-PUF.