Patents by Inventor Mohammad Waseem
Mohammad Waseem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250140620Abstract: In examples, a method for manufacturing a package comprises depositing a metal contact layer on a surface of a wafer, the wafer including first and second diodes; positioning the wafer on an expandable tape coupled to a carrier; dicing the wafer to produce first and second dies, the first die including the first diode and the second die including the second diode; wire bonding the first die to the second die using a bond wire; covering the first and second dies and the bond wire with a mold compound to produce a molded structure; decoupling the molded structure from the expandable tape; and sawing the molded structure to produce the package.Type: ApplicationFiled: October 31, 2023Publication date: May 1, 2025Inventors: Thomas KRONENBERG, Mohammad WASEEM HUSSAIN
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Publication number: 20250022781Abstract: A multi-chip module (MCM) package includes a leadframe including half-etched lead terminals including a full-thickness and half-etched portion, and second lead terminals including a thermal pad(s). A first die is attached by a dielectric die attach material to the half-etched lead terminals. The first die includes first bond pads coupled to first circuitry configured for receiving a control signal and for outputting a coded signal and a transmitter. The second die includes second bond pads coupled to second circuitry configured for a receiver with a gate driver. The second die is attached by a conductive die attach material to the thermal pad. Bond wires include die-to-die bond wires between a portion of the first and second bond pads. A high-voltage isolation device is between the transmitter and receiver. A mold compound encapsulates the first and the second die.Type: ApplicationFiled: September 30, 2024Publication date: January 16, 2025Inventors: Matthew David Romig, Wei Zhang, Mohammad Waseem Hussain, Peter Anthony Fundaro
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Patent number: 12142550Abstract: A multi-chip module (MCM) package includes a leadframe including half-etched lead terminals including a full-thickness and half-etched portion, and second lead terminals including a thermal pad(s). A first die is attached by a dielectric die attach material to the half-etched lead terminals. The first die includes first bond pads coupled to first circuitry configured for receiving a control signal and for outputting a coded signal and a transmitter. The second die includes second bond pads coupled to second circuitry configured for a receiver with a gate driver. The second die is attached by a conductive die attach material to the thermal pad. Bond wires include die-to-die bond wires between a portion of the first and second bond pads. A high-voltage isolation device is between the transmitter and receiver. A mold compound encapsulates the first and the second die.Type: GrantFiled: December 22, 2022Date of Patent: November 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Matthew David Romig, Wei Zhang, Mohammad Waseem Hussain, Peter Anthony Fundaro
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Patent number: 11855001Abstract: A semiconductor device package includes a leadless leadframe, and a plurality of terminal pads extending to a periphery of the leadframe. At least two of the plurality of terminal pads are interior extending terminal pads that include an interior portion having a shape including at least one curved portion and an exterior portion that extends to the periphery of the leadframe. An integrated circuit (IC) die having at least a semiconductor surface includes circuitry configured for at least one function having nodes connected to bond pads on the leadframe. There is a bonding arrangement between the plurality of terminal pads and the bond pads. A mold compound is for encapsulation of the semiconductor device package.Type: GrantFiled: November 4, 2020Date of Patent: December 26, 2023Assignee: Texas Instruments IncorporatedInventors: Mohammad Waseem Hussain, David Taiwai Chin, Dorothy Lyou Mantle
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Publication number: 20230129232Abstract: A multi-chip module (MCM) package includes a leadframe including half-etched lead terminals including a full-thickness and half-etched portion, and second lead terminals including a thermal pad(s). A first die is attached by a dielectric die attach material to the half-etched lead terminals. The first die includes first bond pads coupled to first circuitry configured for receiving a control signal and for outputting a coded signal and a transmitter. The second die includes second bond pads coupled to second circuitry configured for a receiver with a gate driver. The second die is attached by a conductive die attach material to the thermal pad. Bond wires include die-to-die bond wires between a portion of the first and second bond pads. A high-voltage isolation device is between the transmitter and receiver. A mold compound encapsulates the first and the second die.Type: ApplicationFiled: December 22, 2022Publication date: April 27, 2023Inventors: Matthew David Romig, Wei Zhang, Mohammad Waseem Hussain, Peter Anthony Fundaro
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Patent number: 11569154Abstract: An electronic device includes a package structure, a first lead and a second lead. The first lead has a first portion extending outward from a side of the package structure and downward, and a second portion extending outward from the first portion away from the package side. The second lead has a first portion extending outward from the package side and downward, and a second portion extending inward from the first portion toward the package side, and a distal end of the second lead is spaced from the package side.Type: GrantFiled: May 27, 2021Date of Patent: January 31, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad Waseem Hussain, Anis Fauzi Bin Abdul Aziz
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Patent number: 11538741Abstract: A multi-chip module (MCM) package includes a leadframe including half-etched lead terminals including a full-thickness and half-etched portion, and second lead terminals including a thermal pad(s). A first die is attached by a dielectric die attach material to the half-etched lead terminals. The first die includes first bond pads coupled to first circuitry configured for receiving a control signal and for outputting a coded signal and a transmitter. The second die includes second bond pads coupled to second circuitry configured for a receiver with a gate driver. The second die is attached by a conductive die attach material to the thermal pad. Bond wires include die-to-die bond wires between a portion of the first and second bond pads. A high-voltage isolation device is between the transmitter and receiver. A mold compound encapsulates the first and the second die.Type: GrantFiled: February 17, 2021Date of Patent: December 27, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Matthew David Romig, Wei Zhang, Mohammad Waseem Hussain, Peter Anthony Fundaro
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Publication number: 20220384317Abstract: An electronic device includes a package structure, a first lead and a second lead. The first lead has a first portion extending outward from a side of the package structure and downward, and a second portion extending outward from the first portion away from the package side. The second lead has a first portion extending outward from the package side and downward, and a second portion extending inward from the first portion toward the package side, and a distal end of the second lead is spaced from the package side.Type: ApplicationFiled: May 27, 2021Publication date: December 1, 2022Applicant: Texas Instruments IncorporatedInventors: Mohammad Waseem Hussain, Anis Fauzi Bin Abdul Aziz
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Patent number: 11410913Abstract: A packaged electrical device that includes a cured adhesive layer and a cured layer of die attach material coupled between a semiconductor die and a substrate. The packaged electrical device may also include wire bonds coupled between the substrate and leads of the semiconductor die. In addition, the packaged electrical device may be encapsulated in molding compound. A method for fabricating a packaged electrical device. The method includes printing a layer of die attach material over a semiconductor wafer and applying a layer of 2-in-1 die attach film over the layer of die attach material. The method also includes singulating the semiconductor wafer to create a semiconductor die and placing the semiconductor die onto a substrate. In addition the method includes wire bonding the substrate to leads of the semiconductor die and encapsulating the device in molding compound.Type: GrantFiled: March 18, 2020Date of Patent: August 9, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad Waseem Hussain, Steven Murphy, Leslie E. Stark
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Publication number: 20220139847Abstract: A semiconductor device package includes a leadless leadframe, and a plurality of terminal pads extending to a periphery of the leadframe. At least two of the plurality of terminal pads are interior extending terminal pads that include an interior portion having a shape including at least one curved portion and an exterior portion that extends to the periphery of the leadframe. An integrated circuit (IC) die having at least a semiconductor surface includes circuitry configured for at least one function having nodes connected to bond pads on the leadframe. There is a bonding arrangement between the plurality of terminal pads and the bond pads. A mold compound is for encapsulation of the semiconductor device package.Type: ApplicationFiled: November 4, 2020Publication date: May 5, 2022Inventors: Mohammad Waseem Hussain, David Taiwai Chin, Dorothy Lyou Mantle
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Publication number: 20210257282Abstract: A multi-chip module (MCM) package includes a leadframe including half-etched lead terminals including a full-thickness and half-etched portion, and second lead terminals including a thermal pad(s). A first die is attached by a dielectric die attach material to the half-etched lead terminals. The first die includes first bond pads coupled to first circuitry configured for receiving a control signal and for outputting a coded signal and a transmitter. The second die includes second bond pads coupled to second circuitry configured for a receiver with a gate driver. The second die is attached by a conductive die attach material to the thermal pad. Bond wires include die-to-die bond wires between a portion of the first and second bond pads. A high-voltage isolation device is between the transmitter and receiver. A mold compound encapsulates the first and the second die.Type: ApplicationFiled: February 17, 2021Publication date: August 19, 2021Inventors: Matthew David Romig, Wei Zhang, Mohammad Waseem Hussain, Peter Anthony Fundaro
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Publication number: 20200219798Abstract: A packaged electrical device that includes a cured adhesive layer and a cured layer of die attach material coupled between a semiconductor die and a substrate. The packaged electrical device may also include wire bonds coupled between the substrate and leads of the semiconductor die. In addition, the packaged electrical device may be encapsulated in molding compound. A method for fabricating a packaged electrical device. The method includes printing a layer of die attach material over a semiconductor wafer and applying a layer of 2-in-1 die attach film over the layer of die attach material. The method also includes singulating the semiconductor wafer to create a semiconductor die and placing the semiconductor die onto a substrate. In addition the method includes wire bonding the substrate to leads of the semiconductor die and encapsulating the device in molding compound.Type: ApplicationFiled: March 18, 2020Publication date: July 9, 2020Inventors: Mohammad Waseem Hussain, Steven Murphy, Leslie E. Stark
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Patent number: 10636727Abstract: A packaged electrical device that includes a cured adhesive layer and a cured layer of die attach material coupled between a semiconductor die and a substrate. The packaged electrical device may also include wire bonds coupled between the substrate and leads of the semiconductor die. In addition, the packaged electrical device may be encapsulated in molding compound. A method for fabricating a packaged electrical device. The method includes printing a layer of die attach material over a semiconductor wafer and applying a layer of 2-in-1 die attach film over the layer of die attach material. The method also includes singulating the semiconductor wafer to create a semiconductor die and placing the semiconductor die onto a substrate. In addition the method includes wire bonding the substrate to leads of the semiconductor die and encapsulating the device in molding compound.Type: GrantFiled: February 19, 2018Date of Patent: April 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad Waseem Hussain, Steven Murphy, Leslie E. Stark
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Publication number: 20190259685Abstract: A packaged electrical device that includes a cured adhesive layer and a cured layer of die attach material coupled between a semiconductor die and a substrate. The packaged electrical device may also include wire bonds coupled between the substrate and leads of the semiconductor die. In addition, the packaged electrical device may be encapsulated in molding compound. A method for fabricating a packaged electrical device. The method includes printing a layer of die attach material over a semiconductor wafer and applying a layer of 2-in-1 die attach film over the layer of die attach material. The method also includes singulating the semiconductor wafer to create a semiconductor die and placing the semiconductor die onto a substrate. In addition the method includes wire bonding the substrate to leads of the semiconductor die and encapsulating the device in molding compound.Type: ApplicationFiled: February 19, 2018Publication date: August 22, 2019Inventors: Mohammad Waseem Hussain, Steven Murphy, Leslie E. Stark
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Patent number: 9961099Abstract: This disclosure is related to using network flow information of a network to determine the trajectory of an attack. In some examples, an adjacency data structure is generated for a network. The adjacency data structure can include a machine of the network that has interacted with another machine of the network. The network can further include one or more deception mechanisms. The deception mechanisms can indicate that an attack is occurring when a machine interacts with one of the deception mechanisms. When the attack is occurring, attack trajectory information can be generated by locating in the adjacency data structure the machine that interacted with the deception mechanism. The attack trajectory information can correlate the information from the interaction with the deception mechanism, the interaction information of the network, and machine information for each machine to determine a possible trajectory of an adversary.Type: GrantFiled: February 7, 2017Date of Patent: May 1, 2018Assignee: ACALVIO TECHNOLOGIES, INC.Inventors: Satnam Singh, Mohammad Waseem, Suril Desai, Venkata Babji Sama, Rajendra Gopalakrishna
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Publication number: 20170302691Abstract: This disclosure is related to using network flow information of a network to determine the trajectory of an attack. In some examples, an adjacency data structure is generated for a network. The adjacency data structure can include a machine of the network that has interacted with another machine of the network. The network can further include one or more deception mechanisms. The deception mechanisms can indicate that an attack is occurring when a machine interacts with one of the deception mechanisms. When the attack is occurring, attack trajectory information can be generated by locating in the adjacency data structure the machine that interacted with the deception mechanism. The attack trajectory information can correlate the information from the interaction with the deception mechanism, the interaction information of the network, and machine information for each machine to determine a possible trajectory of an adversary.Type: ApplicationFiled: February 7, 2017Publication date: October 19, 2017Applicant: Acalvio Technologies, Inc.Inventors: Satnam Singh, Mohammad Waseem, Suril Desai, Venkata Babji Sama, Rajendra Gopalakrishna
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Patent number: 8996334Abstract: A method and a system for analyzing turbomachinery is provided. In one embodiment, a system for analyzing turbomachinery is provided. The system includes an intelligent turbomachinery tracking filter (ITTF) system configured to determine one or more performance shifts for one or more components of the turbomachinery based on a plurality of turbomachinery parameters. The system further includes a root cause analyzer configured to determine a root cause of the turbomachinery performance based on the one or more performance shifts. The one or more performance shifts include trended data.Type: GrantFiled: March 2, 2011Date of Patent: March 31, 2015Assignee: General Electric CompanyInventors: Adriana Elizabeth Trejo Sanchez, Mohammad Waseem Adhami, Jose Leon Vega Paez, Monica Lizbeth Perez Gamboa, Juan Paulo Chavez Valdovinos
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Publication number: 20130024179Abstract: A system, in one embodiment, provides means for acquired measurements of one or more operating parameters of a turbine engine. The system further includes means for determining an estimated value of a performance parameter of interest at a current time based at least partially upon the acquired measurements, means for adjusting a deterioration model at the current time based on a historical set of estimated values from previous times, and means for forecasting performance changes in the turbine engine based on the adjusted deterioration model.Type: ApplicationFiled: July 22, 2011Publication date: January 24, 2013Applicant: GENERAL ELECTRIC COMPANYInventors: Maria Cecilia Mazzaro, Mohammad Waseem Adhami, Juan Paulo Chavez Valdovinos, Achalesh Kumar Pandey, Atanu Talukdar, Adriana Elizabeth Trejo, Jose Vega Paez
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Publication number: 20120226474Abstract: A method and a system for analyzing turbomachinery is provided. In one embodiment, a system for analyzing turbomachinery is provided. The system includes an intelligent turbomachinery tracking filter (ITTF) system configured to determine one or more performance shifts for one or more components of the turbomachinery based on a plurality of turbomachinery parameters. The system further includes a root cause analyzer configured to determine a root cause of the turbomachinery performance based on the one or more performance shifts. The one or more performance shifts include trended data.Type: ApplicationFiled: March 2, 2011Publication date: September 6, 2012Applicant: General Electric CompanyInventors: Adriana Elizabeth Trejo Sanchez, Mohammad Waseem Adhami, Jose Leon Vega Paez, Monica Lizbeth Perez Gamboa, Juan Paulo Chavez Valdovinos
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Publication number: 20110142602Abstract: Variable elements of a turbine engine such as variable inlet guide vanes, variable bleed valves and variable stator vanes can be adjusted to provide a desired level of power and/or efficiency for the turbine engine across a range of operating conditions. The variable element settings typically determined through experimentation when the engine is new. Unfortunately, over the life cycle of the turbine engine, as wear occurs, the original variable element settings may no longer provide a desired level of power and efficiency. To correct this problem, offsets to the original variable element settings are calculated based on observable operational conditions which provide a measure of the wear that has occurred. The offsets are applied to the original variable element settings to generate corrected variable element settings. These corrected variable element settings are then used to configure the turbine engine.Type: ApplicationFiled: December 15, 2009Publication date: June 16, 2011Inventors: Mohammad Waseem ADHAMI, Stephen Bartlett, Robert Coleman, Kenneth Meiners