Abstract: Apparatus and associated methods relate to a system or method of precision battery charge measurement. Some embodiments may include precise charge and discharge control based on precision battery voltage and current sensing. In an illustrative example, energy either going in or out of the battery may be multiplied or computed using novel circuitry. In various embodiments, energy may be computed in a precision energy small unit determined as a percentage of total battery capacity. In an illustrative example, the precision unit may be, for example, 0.0018% of the total battery capacity. In some embodiments, the energy meter value may be in digital form, so it can be stored in memory and transmitted to external users as desired using USB type C or any other method. Various embodiments may advantageously provide extended battery life, based on using the measured energy meter value to maintain the state of charge of the battery.

Abstract: Apparatus and associated methods relate to configuring a circuit to sense current in a low-cost non-precision resistance, calibrating the circuit to correct inaccuracy measured in the sensed current, and measuring with the corrected circuit the precise current sensed in the low-cost non-precision resistance. In an illustrative example, the low-cost non-precision resistance may be a metal trace on a printed circuit board. The circuit may be calibrated, for example, over a range of currents or temperatures, permitting automatic adjustment to a wide range of non-precision resistance parameter values and environmental conditions. In some examples, correcting coefficients may be adapted to compensate for resistance non-linearities, which may include skin effect or self-heating. Some embodiments may verify the calibrated correction over a range of current and temperature.

Abstract: Apparatus and associated methods relate to a system or method of precision battery charge measurement. Some embodiments may include precise charge and discharge control based on precision battery voltage and current sensing. In an illustrative example, energy either going in or out of the battery may be multiplied or computed using novel circuitry. In various embodiments, energy may be computed in a precision energy small unit determined as a percentage of total battery capacity. In an illustrative example, the precision unit may be, for example, 0.0018% of the total battery capacity. In some embodiments, the energy meter value may be in digital form, so it can be stored in memory and transmitted to external users as desired using USB type C or any other method. Various embodiments may advantageously provide extended battery life, based on using the measured energy meter value to maintain the state of charge of the battery.

Abstract: Apparatus and associated methods relate to configuring a circuit to sense current in a low-cost non-precision resistance, calibrating the circuit to correct inaccuracy measured in the sensed current, and measuring with the corrected circuit the precise current sensed in the low-cost non-precision resistance. In an illustrative example, the low-cost non-precision resistance may be a metal trace on a printed circuit board. The circuit may be calibrated, for example, over a range of currents or temperatures, permitting automatic adjustment to a wide range of non-precision resistance parameter values and environmental conditions. In some examples, correcting coefficients may be adapted to compensate for resistance non-linearities, which may include skin effect or self-heating. Some embodiments may verify the calibrated correction over a range of current and temperature.

Abstract: A method for manufacturing a Micro-Electro-Mechanical System pressure sensor, including forming a gauge wafer including a diaphragm and a pedestal region. The method includes forming an electrical insulation layer disposed on a second surface of the diaphragm region and forming a plurality of sensing elements patterned on the electrical insulation layer disposed on the second surface in the diaphragm region, forming a cap wafer with a central recess in an inner surface and a plurality of through-wafer embedded vias made of an electrically conductive material in the cap wafer, creating a sealed cavity by coupling the inner recessed surface of the cap wafer to the gauge wafer, such that electrical connections from the sensing elements come out to an outer surface of the cap wafer through the vias, and attaching a spacer wafer with a central aperture to the pedestal region with the central aperture aligned to the diaphragm region.

Abstract: A Micro-Electro-Mechanical System (MEMS) pressure sensor is disclosed, comprising a gauge wafer, comprising a micromachined structure comprising a membrane region and a pedestal region, wherein a first surface of the micromachined structure is configured to be exposed to a pressure medium that exerts a pressure resulting in a deflection of the membrane region. The gauge wafer also comprises a plurality of sensing elements patterned on the electrical insulation layer on a second surface in the membrane region, wherein a thermal expansion coefficient of the material of the sensing elements substantially matches with a thermal expansion coefficient of the material of the gauge wafer. The pressure sensor comprises a cap wafer coupled to the gauge wafer, which includes a recess on an inner surface of the cap wafer facing the gauge wafer that defines a sealed reference cavity that encloses and prevents exposure of the sensing elements to an external environment.

Abstract: A method for manufacturing a Micro-Electro-Mechanical System pressure sensor, including forming a gauge wafer including a diaphragm and a pedestal region. The method includes forming an electrical insulation layer disposed on a second surface of the diaphragm region and forming a plurality of sensing elements patterned on the electrical insulation layer disposed on the second surface in the diaphragm region, forming a cap wafer with a central recess in an inner surface and a plurality of through-wafer embedded vias made of an electrically conductive material in the cap wafer, creating a sealed cavity by coupling the inner recessed surface of the cap wafer to the gauge wafer, such that electrical connections from the sensing elements come out to an outer surface of the cap wafer through the vias, and attaching a spacer wafer with a central aperture to the pedestal region with the central aperture aligned to the diaphragm region.

Abstract: A method for manufacturing a Micro-Electro-Mechanical System pressure sensor. The method includes forming a gauge wafer including a diaphragm and a pedestal region. The method includes forming an electrical insulation layer disposed on a second surface of the diaphragm region and forming a plurality of sensing elements patterned on the electrical insulation layer disposed on the second surface in the diaphragm region. The method includes forming a cap wafer with a central recess in an inner surface and a plurality of through-wafer embedded vias made of an electrically conductive material in the cap wafer. The method includes creating a sealed cavity by coupling the inner recessed surface of the cap wafer to the gauge wafer, such that electrical connections from the sensing elements come out to an outer surface of the cap wafer through the vias. The method includes attaching a spacer wafer with a central aperture to the pedestal region with the central aperture aligned to the diaphragm region.

Abstract: A method for manufacturing a Micro-Electro-Mechanical System pressure sensor. The method includes forming a gauge wafer including a diaphragm and a pedestal region. The method includes forming an electrical insulation layer disposed on a second surface of the diaphragm region and forming a plurality of sensing elements patterned on the electrical insulation layer disposed on the second surface in the diaphragm region. The method includes forming a cap wafer with a central recess in an inner surface and a plurality of through-wafer embedded vias made of an electrically conductive material in the cap wafer. The method includes creating a sealed cavity by coupling the inner recessed surface of the cap wafer to the gauge wafer, such that electrical connections from the sensing elements come out to an outer surface of the cap wafer through the vias. The method includes attaching a spacer wafer with a central aperture to the pedestal region with the central aperture aligned to the diaphragm region.

Abstract: A pressure sensor is described with sensing elements electrically and physically isolated from a pressurized medium. An absolute pressure sensor has a reference cavity, which can be at a vacuum or zero pressure, enclosing the sensing elements. The reference cavity is formed by bonding a recessed cap wafer with a gauge wafer having a micromachined diaphragm. Sensing elements are disposed on a first side of the diaphragm. The pressurized medium accesses a second side of the diaphragm opposite to the first side where the sensing elements are disposed. A spacer wafer may be used for structural support and stress relief of the gauge wafer. In one embodiment, vertical through-wafer conductive vias are used to bring out electrical connections from the sensing elements to outside the reference cavity. In an alternative embodiment, peripheral bond pads on the gauge wafer are used to bring out electrical connections from the sensing elements to outside the reference cavity.

Abstract: A pressure sensor is described with sensing elements electrically and physically isolated from a pressurized medium. An absolute pressure sensor has a reference cavity, which can be at a vacuum or zero pressure, enclosing the sensing elements. The reference cavity is formed by bonding a recessed cap wafer with a gauge wafer having a micromachined diaphragm. Sensing elements are disposed on a first side of the diaphragm. The pressurized medium accesses a second side of the diaphragm opposite to the first side where the sensing elements are disposed. A spacer wafer may be used for structural support and stress relief of the gauge wafer. In one embodiment, vertical through-wafer conductive vias are used to bring out electrical connections from the sensing elements to outside the reference cavity. In an alternative embodiment, peripheral bond pads on the gauge wafer are used to bring out electrical connections from the sensing elements to outside the reference cavity.

Abstract: A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

Abstract: A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

Abstract: A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

Abstract: According to one embodiment of the invention, a method of packaging flip chips includes providing a plurality of flip chips and a panel, forming a plurality of partitions outwardly from the panel, coupling the flip chips to the panel such that each partition surrounds a respective flip chip, and forming an underfill region between each of the flip chips and the panel. Each partition prevents a respective underfill region from engaging an adjacent underfill region.

Abstract: A patterned plasma treatment may be provided on the chip and/or the substrate to enhance the distribution of underfill material between the chip and the substrate. The underfill material is typically dispensed after the chip is electrically connected to the substrate. The chip may be electrically connected to the substrate by an array of solder bumps, as one example. The underfill material is draw into a gap between the chip and the substrate by a capillary action. The patterned plasma-treated area formed on the chip and/or on the substrate may cause greater capillary force on the underfill material, as compared to non-plasma-treated areas. Such patterned plasma-treatment area may be designed and laid out to provide for more or better control of the underfill distribution between the chip and substrate while forming a chip package.

Abstract: A flip chip optoelectronic device assembly includes a hollow, cylindrical spacer between an optical source in the substrate and the active surface of the chip, which precludes attenuation of the signal and allows direct transmission through air. An underfill material fills the space between chip and substrate, thereby allowing substrates which are not necessarily matched in thermal expansion to the chips, and the spacer acts as a dam to prevent ingress of underfill material into the optical path. The spacer not only allows use of conventional underfill materials to support the interconnection joints and thermal mismatch, but also defines a fixed “z” axis distance between substrate and chip.

Abstract: According to one embodiment of the invention, a method of packaging flip chips includes providing a plurality of flip chips and a panel, forming a plurality of partitions outwardly from the panel, coupling the flip chips to the panel such that each partition surrounds a respective flip chip, and forming an underfill region between each of the flip chips and the panel. Each partition prevents a respective underfill region from engaging an adjacent underfill region.

Abstract: A metallurgical interconnection for electronic devices is described, wherein the interconnection has first and second interconnection metals. The first metal is shaped to enlarge the contact area, thus providing maximum mechanical interconnection strength, and to stop nascent cracks, which propagate in the interconnection. Preferred shapes include castellation and corrugation. The castellation may include metal protrusions, which create wall-like obstacles in the interconnection zones of highest thermomechanical stress, whereby propagating cracks are stopped. The surface of the first metal has an affinity to form metallurgical contacts. The second metal is capable of reflowing. The first metal is preferably copper, and the second metal tin or a tin alloy.

Abstract: Electronic devices of improved reliability having a substrate of electrically insulating material, further an integrated circuit chip with a periphery and a surface. Using a layer of polymeric material, the chip surface is mounted on the substrate surface. The polymeric material protrudes beyond the chip periphery and spreads some distance along the substrate surface. A metal layer is on the substrate surface, this layer is shaped as a band around the chip periphery; the band has an inner edge near the chip periphery, and an outer edge near the contour of the polymer protrusion. This metal band serves as a guard ring to stop any nascent crack propagating in the polymer protrusion.