Patents by Inventor Mohammadhassan Najafi
Mohammadhassan Najafi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250046074Abstract: A method and architecture for encoding image data solely based on pixel intensities, eliminating the need for encoding pixel positions. This is achieved by utilizing low-discrepancy (LD) sequences, such as Sobol or Van Der Corput (VDC) sequences, for deterministic encoding of the image intensity values. The position hypervectors, which were previously required for representing pixel positions, are no longer needed. The corresponding index of the LD sequence is used to encode the intensity values.Type: ApplicationFiled: July 31, 2024Publication date: February 6, 2025Applicant: University of Louisiana at LafayetteInventors: Mohammadhassan NAJAFI, Mehran Moghadam, Sercan Aygun
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Publication number: 20250014325Abstract: Disclosed herein a method for agile simulation of a stochastic computing image processing where the input operands are processed with the aid of a correlation-controlled contingency table (CT) construct without using actual stochastic bit-streams. The disclosed method utilizes contingency tables to perform (i) template matching, (ii) image compositing, and (iii) pattern detection. Results show that the proposed approach achieves similar computation accuracy to the traditional stochastic computing simulation while performing runtime- and memory-efficient computations.Type: ApplicationFiled: July 5, 2024Publication date: January 9, 2025Applicant: UNIVERSITY OF LOUISIANA LAFAYETTEInventors: Mohammadhassan NAJAFI, Sercan Aygun, Ece Olca Gunes
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Patent number: 12045166Abstract: Disclosed herein is an architecture for in-memory sorting of data and methods by utilizing memristors crossbar arrays to perform in-memory sorting for both unary bit-stream and binary format data sets and method for utilizing same. Evaluations of the disclosed architecture and method reflect a significant reduction in energy costs and processing time as compared to currently available solutions.Type: GrantFiled: December 13, 2022Date of Patent: July 23, 2024Assignee: University of Louisiana at LafayetteInventors: Mohammadhassan Najafi, Mohsen Riahi Alam, Nima Taherinejad
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Publication number: 20230195621Abstract: Disclosed herein is an architecture for in-memory sorting of data and methods by utilizing memristors crossbar arrays to perform in-memory sorting for both unary bit-stream and binary format data sets and method for utilizing same. Evaluations of the disclosed architecture and method reflect a significant reduction in energy costs and processing time as compared to currently available solutions.Type: ApplicationFiled: December 13, 2022Publication date: June 22, 2023Applicant: UNIVERSITY OF LOUISIANA LAFAYETTEInventors: Mohammadhassan NAJAFI, Mohsen Riahi Alam, Nima Taherinejad
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Publication number: 20230025438Abstract: Disclosed herein is a low-cost finite state machine-based low-discrepancy bit-stream generator that support generation of any number of independent low-discrepancy bit-streams. Here, the order of bit selection by the FSM of the bit-stream generator is determined based on the distribution of numbers in the Sobol sequences. An independent LD bit-stream is generated by setting up the FSM using a different Sobol sequence. The proposed generator reduces the hardware costs by more than 80 percent compared to the low-discrepancy bit-stream generators known in the art. The available space can then be used to improve fault tolerance.Type: ApplicationFiled: July 15, 2022Publication date: January 26, 2023Applicant: University of Louisiana at LafayetteInventors: Mohammadhassan Najafi, Mohsen Imani, Sina Asadi
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Publication number: 20220334800Abstract: The multiplication method disclosed herein benefits from the complementary advantages of both Stochastic Computing (SC) and memristive In-Memory Computation (IMC) to enable energy-efficient and low-latency multiplication of data. In summary, the following method are disclosed. (a) Performing deterministic and accurate bit-stream-based multiplication in memory. To this end, the invention disclosed herein uses memristive crossbar memory arrays and Memory-Aided Logic (MAGIC). (b) Using an efficient in-memory method for generating deterministic bit-streams from binary data, which takes advantage of inherent properties of memristive memories. (c) Improving the speed and reducing the memory usage as compared to the State-of-the-Art (SoA) limited-precision in-memory binary multipliers. (d) Reducing latency and energy consumption compared to the SoA accurate off-memory SC multiplication techniques.Type: ApplicationFiled: April 19, 2022Publication date: October 20, 2022Applicant: UNIVERSITY OF LOUISIANA AT LAFAYETTEInventors: Mohammadhassan Najafi, Mohsen Riahi Alam, Nima TaheriNejad
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Patent number: 11475288Abstract: Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.Type: GrantFiled: November 5, 2019Date of Patent: October 18, 2022Assignee: Regents of the University of MinnesotaInventors: Mohammadhassan Najafi, David J. Lilja, Marcus Riedel, Kiarash Bazargan
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Patent number: 11275563Abstract: Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.Type: GrantFiled: June 19, 2020Date of Patent: March 15, 2022Assignee: Regents of the University of MinnesotaInventors: Mohammadhassan Najafi, David J. Lilja, Marcus Riedel, Kiarash Bazargan, Sayed Abdolrasoul Faraji, Bingzhe Li
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Publication number: 20210383264Abstract: Efficient hardware design of the fuzzy-inference engine has become necessary for high-performance applications. The disclosed technology applies unary processing to the platform of fuzzy-logic. To mitigate the latency, the proposed design processes right-aligned bit-streams. A one-hot decoder is used for fast detection of the bit-stream with maximum value. Implementing a fuzzy-inference engine with 81 fuzzy-inference rules, the disclosed architecture provides 82%, 46%, and 67% saving in the hardware area, power and energy consumption, respectively, and 94% reduction in the number of used LUTs compared to conventional binary implementation.Type: ApplicationFiled: June 7, 2021Publication date: December 9, 2021Applicant: University of Louisiana at LafayetteInventors: Mohammadhassan Najafi, Amir Hossein Jalilvand, Mahdi Fazeli
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Publication number: 20210256357Abstract: The disclosed invention provides a novel architecture that reduces the computation time of stochastic computing-based multiplications in the convolutional layers of convolutional neural networks (CNNs). Each convolution in a CNN is composed of numerous multiplications where each input value is multiplied by a weight vector. Subsequent multiplications are performed by multiplying the input and differences of the successive weights. Leveraging this property, disclosed is a differential Multiply-and-Accumulate unit to reduce the time consumed by convolutions in the architecture. The disclosed architecture offers 1.2× increase in speed and 2.7× increase in energy efficiency compared to known convolutional neural networks.Type: ApplicationFiled: January 27, 2021Publication date: August 19, 2021Inventors: Mohammadhassan Najafi, Seved Reza Hojabrossadati, Kamyar Givaki, S.M. Reza Tayaranian, Parsa Esfahanian, Ahmad Khonsari, Dara Rahmati
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Publication number: 20210241085Abstract: Inaccuracy of computations is an important challenge with the Stochastic Computing (SC) paradigm. Recently, deterministic approaches to SC are proposed to produce completely accurate results with SC circuits. Instead of random bit-streams, the computations are performed on structured deterministic bit-streams. However, current deterministic methods take a large number of clock cycles to produce correct result. This long processing time directly translates to very high energy consumption. This invention proposes a design methodology based on the Residue Number Systems (RNS) to mitigate the long processing time of the deterministic methods. Compared to the state-of-the-art deterministic methods of SC, the proposed approach delivers improvements in terms of processing time and energy consumption.Type: ApplicationFiled: February 3, 2021Publication date: August 5, 2021Inventors: Mohammadhassan Najafi, Kamyar Givaki, Seyed Reza Hojabrossadati, M.H. Gholamrezayi, Ahmad Khonsari, Saeid Gorgin, Dara Rahmati
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Patent number: 10996929Abstract: This disclosure describes techniques for processing data bits using pseudo-random deterministic bit-streams. In some examples, a device includes a pseudo-random bit-stream generator configured to generate bit combinations encoding first and second numerical values based on a proportion of the data bits in the sequence that are high relative to the total data bits in the sequence. The device also includes a stochastic computational unit configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation, wherein the data bits of the output bit-stream represent the result based on a probability that any data bit in the set of data bits of the output bit-stream is high.Type: GrantFiled: March 14, 2019Date of Patent: May 4, 2021Assignee: Regents of the University of MinnesotaInventors: Mohammadhassan Najafi, David J. Lilja
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Publication number: 20200401376Abstract: Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.Type: ApplicationFiled: June 19, 2020Publication date: December 24, 2020Inventors: Mohammadhassan Najafi, David J. Lilja, Marcus Riedel, Kiarash Bazargan, Sayed Abdolrasoul Faraji, Bingzhe Li
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Patent number: 10740686Abstract: Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.Type: GrantFiled: January 12, 2018Date of Patent: August 11, 2020Assignee: Regents of the University of MinnesotaInventors: Mohammadhassan Najafi, Shiva Jamalizavareh, David J. Lilja, Marcus Riedel, Kiarash Bazargan, Ramesh Harjani
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Publication number: 20200143234Abstract: Various implementations of sorting networks are described that utilize time-encoded data signals having encoded values. In some examples, an electrical circuit device includes a sorting network configured to receive a plurality of time-encoded signals. Each time-encoded signal of the plurality of time-encoded signals encodes a data value based on a duty cycle of the respective time-encoded signal or based on a proportion of data bits in the respective time-encoded signal that are high relative to the total data bits in the respective time-encoded signal. The sorting network is also configured to sort the plurality of time-encoded signals based on the encoded data values of the plurality of time-encoded signals.Type: ApplicationFiled: November 5, 2019Publication date: May 7, 2020Inventors: Mohammadhassan Najafi, David J. Lilja, Marcus Riedel, Kiarash Bazargan
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Patent number: 10520975Abstract: In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.Type: GrantFiled: March 3, 2017Date of Patent: December 31, 2019Assignee: Regents of the University of MinnesotaInventors: David J. Lilja, Mohammadhassan Najafi, Marcus Riedel, Kiarash Bazargan
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Publication number: 20190289345Abstract: This disclosure describes techniques for processing data bits using pseudo-random deterministic bit-streams. In some examples, a device includes a pseudo-random bit-stream generator configured to generate bit combinations encoding first and second numerical values based on a proportion of the data bits in the sequence that are high relative to the total data bits in the sequence. The device also includes a stochastic computational unit configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation, wherein the data bits of the output bit-stream represent the result based on a probability that any data bit in the set of data bits of the output bit-stream is high.Type: ApplicationFiled: March 14, 2019Publication date: September 19, 2019Inventors: Mohammadhassan Najafi, David J. Lilja
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Publication number: 20180204131Abstract: Devices and techniques are described in which stochastic computation is performed on analog periodic pulse signals instead of random, stochastic digital bit streams. Exploiting pulse width modulation (PWM), time-encoded signals corresponding to specific values are generated by adjusting the frequency (period) and duty cycles of PWM signals. With this approach, the latency, area, and energy consumption are all greatly reduced, as compared to prior stochastic approaches. Circuits synthesized with the proposed approach can work as fast and energy efficiently as a conventional binary design while retaining the fault-tolerance and low-cost advantages of conventional stochastic designs.Type: ApplicationFiled: January 12, 2018Publication date: July 19, 2018Inventors: Mohammadhassan Najafi, Shiva Jamalizavareh, David J. Lilja, Marcus Riedel, Kiarash Bazargan, Ramesh Harjani
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Publication number: 20170255225Abstract: In some examples, a device includes an integrated circuit and two or more computational units configured to process respective stochastic bit streams in accordance with respective input clocks. Each of the stochastic bit streams comprises sequential sets of data bits, each of the sets of data bits representing a numerical value based on a probability that any bit in the respective set of data bits is one. The respective input clocks for each of the two or more computational units are unsynchronized.Type: ApplicationFiled: March 3, 2017Publication date: September 7, 2017Inventors: David J. Lilja, Mohammadhassan Najafi, Marcus Riedel, Kiarash Bazargan