Abstract: An example apparatus comprises instruction execution circuitry and fetch circuitry to fetch, from memory, instructions for execution by the instruction execution circuitry. The fetch circuitry comprises a plurality of prediction components, each prediction component being configured to predict instructions in anticipation of the predicted instructions being required for execution by the instruction execution circuitry. The fetch circuitry is configured to fetch instructions in dependence on the predicting. The apparatus further comprises prediction tracking circuitry to maintain, for each of a plurality of execution regions, a prediction performance metric for each prediction component. The fetch circuitry is configured, based on at least one of the prediction performance metrics for a given execution region, to implement a prediction adjustment action in respect of at least one of the prediction components.

Abstract: Circuitry comprises data handling circuitry having a memory, the data handling circuitry being operable in a primary mode in which the data handling circuitry performs a data handling function by accessing the memory and in a secondary mode in which the data handling circuitry performs the data handling function independently of the memory; test circuitry to control a test operation during execution of a set of data processing instructions by a data processor configured to execute data processing instructions by reference to the data handling function performed by the data handling circuitry; in which: the test circuitry is configured to control the data handling circuitry to transition from the primary mode to the secondary mode in response to initiation of a test operation on the memory so that the data processor executes one or more of the set of data processing instructions by reference to the data handling function performed by the data handling circuitry in the secondary mode at least while the test ope

Abstract: Circuitry comprises data handling circuitry having a memory, the data handling circuitry being operable in a primary mode in which the data handling circuitry performs a data handling function by accessing the memory and in a secondary mode in which the data handling circuitry performs the data handling function independently of the memory; test circuitry to control a test operation during execution of a set of data processing instructions by a data processor configured to execute data processing instructions by reference to the data handling function performed by the data handling circuitry; in which: the test circuitry is configured to control the data handling circuitry to transition from the primary mode to the secondary mode in response to initiation of a test operation on the memory so that the data processor executes one or more of the set of data processing instructions by reference to the data handling function performed by the data handling circuitry in the secondary mode at least while the test ope

Abstract: Aspects of the present disclosure relate to an apparatus comprising instruction execution circuitry and fetch circuitry to fetch, from memory, instructions for execution by the instruction execution circuitry. The fetch circuitry comprises a plurality of prediction components, each prediction component being configured to predict instructions in anticipation of the predicted instructions being required for execution by the instruction execution circuitry. The fetch circuitry is configured to fetch instructions in dependence on the predicting. The apparatus further comprises prediction tracking circuitry to maintain, for each of a plurality of execution regions, a prediction performance metric for each prediction component. The fetch circuitry is configured, based on at least one of the prediction performance metrics for a given execution region, to implement a prediction adjustment action in respect of at least one of the prediction components.