Abstract: Provided are systems, methods, and apparatuses for computational offload to storage systems. The method can include a first processing element issuing a first request to the storage device; a storage device, responsive to the first request, obtaining first data on the storage device and providing the first data to the first memory for storage; the second processing element reading the first data from the first memory and performing at least one of an operation or a computation on the first data to generate second data; and the second processing element providing the second data to the first processing element.

Abstract: A device is disclosed. A receiver may receive a portion using a first data format from a source device. A transformation unit may transform the portion into a transformed portion. The transformed portion may use a second data format. A transmitter may deliver the transformed portion to a destination device.

Abstract: A system and method for in-storage video processing. In some embodiments, the system includes a computational storage device, the computational storage device including non-volatile storage and a processing circuit. The processing circuit may be configured to process a first data unit and to process a second data unit, in parallel with the first data unit.

Abstract: A device may include memory media configured as cache media; and one or more circuits configured to perform operations including receiving memory access information, performing a mixture model analysis based on the memory access information to produce one or more scores, and updating the memory media based on the one or more scores. The memory media may include determining that at least one of the one or more scores is above a threshold and loading a portion of memory corresponding to the at least one of the one or more scores to the memory media. Updating the memory media may include determining that at least one of the one or more scores is below a threshold and removing a portion of memory corresponding to the at least one of the one or more scores from the memory media.

Abstract: Systems and methods for parallel data processing. In some embodiments, the system includes: a first processing chain; and a second processing chain, the first processing chain including: a first core; a second core; and a first inter-core bus connecting the second core of the first processing chain to the first core of the first processing chain the system being configured to forward an output of a calculation of the first processing chain to the second processing chain.

Abstract: A memory device is disclosed. The memory device may include an interface to connect the memory device to a processor, a first storage for a data, and a second storage for the data. A controller may process a request received from the processor via the interface using the first storage or the second storage. A policy engine may instruct the controller regarding a storing of the data in the first storage or the second storage.

Abstract: A device is disclosed. An interface may connect the device to a processor. The interface may support a first protocol. A first storage and a second storage may the data. The second storage may support a second protocol different from the first protocol. A controller may be connected to the interface and the first storage. A bridge may be connected to the interface, the first storage, and the second storage. The bridge may include a filter configured to coordinate a data transfer between the first storage and the second storage.

Abstract: A device is disclosed. A receiver may receive a portion using a first data format from a source device. A transformation unit may transform the portion into a transformed portion. The transformed portion may use a second data format. A transmitter may deliver the transformed portion to a destination device.

Abstract: Methods and memory devices are provided in which at least one parser of a memory device converts graph input data into an edge list and a vertex list for a graph database. A merge sorter of the memory device sorts the vertex list to generate a sequential list of vertices. The edge list is converted into a translated list of edges using identifiers (IDs) of the sequential list of vertices. The merge sorter sorts the translated list of edges to generate a sequential list of edges. The graph database is generated using the sequential list of edges.

Abstract: A hardware accelerator for neural network applications can include an image-to-column block and a general matrix-matrix multiplication (GEMM) block. The image-to-column block includes an input controller coupled to receive an input feature map from a memory block; a series of patch units configured in a ring network and coupled to the input controller to receive new elements of the input feature map; and an output controller coupled to receive each output patch from the series of patch units. The GEMM block can be a dynamically reconfigurable unit that can be configured as a tall array or individual square arrays. The described hardware accelerator can handle sparsity in both the feature map inputs (output from the image-to-column block) and the filter/weight inputs to the GEMM block.

Abstract: Provided are systems, methods, and apparatuses for computational offload to storage systems. The method can include a first processing element issuing a first request to the storage device; a storage device, responsive to the first request, obtaining first data on the storage device and providing the first data to the first memory for storage; the second processing element reading the first data from the first memory and performing at least one of an operation or a computation on the first data to generate second data; and the second processing element providing the second data to the first processing element.