Abstract: A device is disclosed. A receiver may receive a portion using a first data format from a source device. A transformation unit may transform the portion into a transformed portion. The transformed portion may use a second data format. A transmitter may deliver the transformed portion to a destination device.

Abstract: Methods and memory devices are provided in which at least one parser of a memory device converts graph input data into an edge list and a vertex list for a graph database. A merge sorter of the memory device sorts the vertex list to generate a sequential list of vertices. The edge list is converted into a translated list of edges using identifiers (IDs) of the sequential list of vertices. The merge sorter sorts the translated list of edges to generate a sequential list of edges. The graph database is generated using the sequential list of edges.

Abstract: A hardware accelerator for neural network applications can include an image-to-column block and a general matrix-matrix multiplication (GEMM) block. The image-to-column block includes an input controller coupled to receive an input feature map from a memory block; a series of patch units configured in a ring network and coupled to the input controller to receive new elements of the input feature map; and an output controller coupled to receive each output patch from the series of patch units. The GEMM block can be a dynamically reconfigurable unit that can be configured as a tall array or individual square arrays. The described hardware accelerator can handle sparsity in both the feature map inputs (output from the image-to-column block) and the filter/weight inputs to the GEMM block.

Abstract: Provided are systems, methods, and apparatuses for computational offload to storage systems. The method can include a first processing element issuing a first request to the storage device; a storage device, responsive to the first request, obtaining first data on the storage device and providing the first data to the first memory for storage; the second processing element reading the first data from the first memory and performing at least one of an operation or a computation on the first data to generate second data; and the second processing element providing the second data to the first processing element.