Abstract: Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture, which is the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected. The architecture disclosed uses a mixture of hardwired and programmable connections for interconnecting the FPGAs. A hardwired connection is a direct connection between a pair of FPGA I/O pins. A programmable connection refers to the scheme in which pair of FPGA I/O pins are connected using an programmable interconnect device. In the architecture disclosed, the I/O pins in each FPGA are divided into two groups: hardwired connections and programmable connections. The pins in the first group connect to other FPGAs and the pins in the second group connect to FPIDs. The FPGAs and FPIDs are interconnected using a partial crossbar architecture.