Abstract: A memory array of four-IGFET-transistor cells arranged in rows and columns. The array uses two patterned metal layers and two patterned poly-silicon layers. For each column there is a pair of metal differential bit lines, formed on a first patterned metal layer. For each row there is a pair of split equipotential poly-silicon word lines and a parallel metal word line with connections to the split poly word lines at defined intervals. The parallel metal word line is on a second patterned metal layer distinct from the metal layer used for the bit lines. A grounded poly-silicon plate overlies the capacitive memory nodes of said array. The grounded poly-silicon plate is on a second patterned poly-silicon layer distinct from the poly-silicon layer used for the split word lines. The poly-silicon plate is connected to the circuit ground at defined intervals. Also, the poly-silicon plate provides alpha particle protection to the array and helps decouple the bit lines from the capacitive nodes of the array.