Abstract: Identifying systematic defects in wafer processing including performing defect inspection of a plurality of wafers, identifying defects in each of the plurality of wafers as not being associated with a trivial and/or known root cause, determining a physical location on each wafer where each of the defects occurs and correlating the physical locations where each of the defects occurs with cell instances defined for those physical locations.

Abstract: Identifying systematic defects in wafer processing including performing defect inspection of a plurality of wafers, identifying defects in each of the plurality of wafers as not being associated with a trivial and/or known root cause, determining a physical location on each wafer where each of the defects occurs and correlating the physical locations where each of the defects occurs with cell instances defined for those physical locations.

Abstract: Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

Abstract: Methods, apparatus and computer program products provide a fast and accurate model for simulating the effects of chemical mechanical polishing (CMP) steps during fabrication of an integrated circuit by generating a design of an integrated circuit; while generating the design of the integrated circuit, using a simplified model to predict at least one physical characteristic of the integrated circuit which results from a CMP processing step to be used during manufacture of the integrated circuit, wherein the simplified model is derived from simulations performed prior to the design generation activities using a comprehensive simulation program used to model the physical characteristic; predicting performance of the integrated circuit using the predicted physical characteristic; and adjusting the design of the integrated circuit in dependence on the performance prediction.

Abstract: A method for automated resource management and optimization, the method includes: monitoring one or more of the following: resource usage, level of resource utilization, and resource amenities; receiving a request for reserving a resource; determining whether the request for the resource is granted as originally requested; wherein the determining of whether to grant the request for resources as originally requested is based one or more thresholds and conditions; wherein the one or more thresholds and conditions are based on the monitoring of at least one of the following: resource usage, the level of resource utilization; and resource amenities; and wherein if the request for reserving a resource fails to meet the one or more thresholds and conditions the request is either denied or modified.

Abstract: A method, apparatus, and computer program product for flattening a warped substrate. The substrate is placed on a planar surface of a clamping apparatus in direct mechanical contact with the planar surface. The substrate comprises surface regions S1, S2, . . . , SN having an average warpage of W1, W2, . . . , WN, respectively, wherein W1?W2? . . . ?WN and W1?WN. Zones Z1, Z2, . . . , ZN of the planar surface respectively comprise vacuum port groups G1, G2, . . . , GN. Each group comprises at least one vacuum port. N is at least 2. A vacuum pressure PV1, PV2, . . . , PVN is generated at each vacuum port within group G1, G2, . . . , GN, at a time of T1, T2, . . . , TN to clamp surface region S1, S2, . . . , SN to zone Z1, Z2, . . . , ZN, respectively. The vacuum pressure PV1, PV2, . . . , PVN is maintained at the vacuum ports of group G1, G2, . . . , GN, respectively, until time TN+1. T1<T2< . . . <TN<TN+1.