Abstract: An integrated circuit (IC) die is provided, which includes a die body; electrostatic discharge (ESD) circuitry formed in the die body; contact pads exposed on an active side of the die body; a first conductive tower formed in the die body and electrically coupling a first contact pad to the ESD circuitry. The first conductive tower comprises first, second, third, and fourth segments formed from metal layers of the die body; a first via electrically coupling the first segment to the second segment; a second via electrically coupling the first segment to the third segment; a third via electrically coupling the second segment to the fourth segment; and a fourth via electrically coupling the third segment to the fourth segment, the second segment electrically parallel with the third segment. The IC die further comprises at least a first data line disposed between the first, second, third, and fourth segments.

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a circuit includes a semiconductor substrate, a first transistor, a second transistor, and a ballast resistor. The semiconductor substrate comprises a p-doped region and an n-doped region. The first transistor comprises an n+ doped source region disposed in the p-doped region of the semiconductor substrate. The second transistor comprises a p+ doped source region disposed in the n-doped region of the semiconductor substrate. The p+ doped source region, the n-doped region, the p-doped region, and the n+ doped source region form a PNPN structure. The ballast resistor is electrically connected in series with the PNPN structure between a power node and a ground node.

Abstract: A circuit for implementing a discharge path in an input/output circuit of an integrated circuit is described. The circuit comprises an input/output pad; a first node coupled to a power reference voltage; a first impedance element implemented between the first node and the input/output pad; a second node coupled to a ground reference voltage; and a second impedance element implemented between the second node and the input/output pad. A method of implementing a discharge path in an input/output circuit of an integrated circuit is also disclosed.

Abstract: A circuit for providing a ground path in an integrated circuit device is described. The circuit comprises a device region formed in a substrate; a substrate tap formed adjacent to the device region; and a conductive path coupled between the substrate tap and a ground metal layer by way of a plurality of metal layers and vias, wherein the conductive path is configured to meet a predetermined design requirement.

Abstract: Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance.

Abstract: A method of evaluating a layout cell for electrostatic discharge (ESD) protection can include identifying at least one feature of the layout cell for use in implementing an integrated circuit (IC) and comparing the at least one feature of the layout cell to an ESD requirement for the IC. The method can include indicating whether the feature of the layout cell complies with the ESD requirement.

Abstract: An embodiment of a semiconductor structure for an electrostatic discharge (“ESD”) protection circuit is disclosed. For this embodiment, there is a substrate of a first polarity type. A device area of the substrate has a source region and a drain region of a transistor. The device area is of the first polarity type, and the source region and the drain region are each of a second polarity type. A well region of the second polarity type surrounds the device area. An outer tap of the first polarity type surrounds the well region, and a bridge interconnects the source region and the outer tap.

Abstract: An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.

Abstract: Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance.

Abstract: An embodiment of the invention involves: providing a database that includes layout information representing a layout within an integrated circuit of an electrical circuit; identifying from the information in the database each conductive path of a selected type in the electrical circuit; extracting layout information from the database for each conductive path of the selected type; and calculating an electrical parameter for each conductive path of the selected type, as a function of the layout information obtained for that conductive path during the extracting. In addition, in a different configuration of the embodiment, a report can be generated containing information based on the electrical parameter calculated during the calculating for at least one of the conductive paths of the selected type.

Abstract: An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground.