Abstract: An array of photon counting phototoreceivers is constructed as an imager with micro-digitized pixels. Each photoreciever comprises a vertical cavity optical amplifier (VCSOA) as an optical amplifier, an avalanche photodiode as detector and an analog-to-digital converter (ADC) in an integrated structure. The ADC serves as a 1-bit digitizer and uses a resonant tunneling bipolar transistor RTBT. While the preferred embodiment of the invention have been described, it will be apparent to those skilled in the art that various modifications may be made to the embodiments without departing from the spirit of the present invention. Such modifications are all within the scope of the present invention.

Abstract: A vertical cavity semiconductor optical photoamplifer (VCSOA) is used as a modulating retro-reflector (MRR) as a pixel in an array. The boundary of the cavity in the VCSOA forms a mirror for reflecting an incident light as an amplified output.

Abstract: Alternate layers of wide band gap and narrow band gaps of different kinds of semiconductors are used to form multiple channels of a FET. The channels are doped or formed as 2-DEG/2-DHG in narrow band semiconductor by charge supply layer in the wide band gap semiconductor. The different kinds of semiconductors form heterojunctions to confine the electrons/holes in separate thin spikes layers. A number of spikes (3-10 nm thick) of different doped or 2-DEG/2-DHG concentrations in various channels can result in overall electron concentration gradient such as a 1/x3 electron/hole concentrations profile. Such an electron/hole concentration gradient can result in a linear variation of drain current with voltage to obtain a wide dynamic range.

Abstract: A varactor having a capacitance includes a depletion mode transistor having a gate, a source, and a drain and an enhancement mode transistor also having a gate, a source, and a drain. The gates of the depletion mode transistor and the enhancement mode transistor are coupled together, the sources of the depletion mode transistor and the enhancement mode transistor are coupled together, and the drains of the depletion mode transistor and the enhancement mode transistor are coupled together. The enhancement mode transistor has a p/n junction. A bias source is coupled to the gates and the sources and drains so as to control the capacitance.

Abstract: One or more electrically conducting vias are formed through a silicon substrate having a first surface, an opposite second surface, and a thickness between the first and second surfaces. A conductive metallic material is deposited on the first surface of the silicon substrate. For example, the metallic material may be deposited at one or more depressions in the first surface at one or more desired via locations. The conductive metallic material is migrated through the silicon substrate from the first surface to the second surface. For example, the conductive metallic material may be thermally migrated, and an oxide layer at the second surface may by used to terminate the migration.

Abstract: A transistor has a first silicon layer comprising a source region and a drain region separated by a channel region. A gate oxide is formed over the first silicon layer. A second silicon layer is formed over the gate oxide and comprises a dual work function gate. The dual work function gate may include p+ and n+ gate regions such that the transistor has different threshold voltages.