Abstract: Described is an apparatus comprising: a voltage level detector to monitor a first power supply node; and a voltage level protector, coupled to the voltage level detector, to protect the voltage level detector from receiving a power supply on the first power supply node above a pre-defined threshold voltage. Described is also a voltage level protector to protect a first power supply node from receiving a power supply above a pre-defined threshold voltage, the voltage level protector comprising: a first p-type device coupled to a second power supply node, the second power supply node to receive a power supply higher than the power supply on the first power supply node; and a second p-type device coupled in series to the first p-type device, the second p-type further coupled to the first power supply node, which is for coupling to a voltage level detector.

Abstract: A memory device includes a first inverter, a second inverter cross-coupled with the first inverter, an accessing unit, and a switching unit. The accessing unit is configured to discharge an output of the first inverter and charge an output of the second inverter according to signals provided by a first word line and a second word line. The switching unit is configured to disconnect a power from the first inverter and the second inverter according to a signal provided by the first word line.

Abstract: A memory device includes a first inverter, a second inverter cross-coupled with the first inverter, an accessing unit, and a switching unit. The accessing unit is configured to discharge an output of the first inverter and charge an output of the second inverter according to signals provided by a first word line and a second word line. The switching unit is configured to disconnect a power from the first inverter and the second inverter according to a signal provided by the first word line.

Abstract: Described is an apparatus comprising: a voltage level detector to monitor a first power supply node; and a voltage level protector, coupled to the voltage level detector, to protect the voltage level detector from receiving a power supply on the first power supply node above a pre-defined threshold voltage. Described is also a voltage level protector to protect a first power supply node from receiving a power supply above a pre-defined threshold voltage, the voltage level protector comprising: a first p-type device coupled to a second power supply node, the second power supply node to receive a power supply higher than the power supply on the first power supply node; and a second p-type device coupled in series to the first p-type device, the second p-type further coupled to the first power supply node, which is for coupling to a voltage level detector.

Abstract: In one embodiment a low voltage high performance memory system is disclosed. The system can include a bit cell, a first pass gate coupled to the bit cell to receive a write signal, a second pass gate coupled to the bit cell to receive the write signal, and an supply current controller to reduce current to at least a portion of the bit cell and to supply current to another portion of the cell in response to a write control signal and a data signal during a bit cell transition. Reducing the current to a portion of the bit cell and supplying current to another portion of the bit cell during transition can allow the bit cell to transition to a different state faster and can reduce the effects of device variations that manifest during low voltage operation. Other embodiments are also disclosed.