Abstract: An input binary member can be modified by one unit with the assistance of an incrementer, composed of a first circuit CL that generates switch signals (p) from the bit places (d) of the input binary number, these switch signals (p) for the least significant digit (d0) being equal to the value of this digit and, at more significant digits, being generated by AND operation out of the less significant bit of the input binary number. The bit digits of the binary output member (A) are generated with the assistance of an output stage to which the input binary number (D) and the digit signals (P) are supplied. The least significant bit digit of the output binary number is acquired by inversion of the least significant bit place of the input binary number. The more significant bit places of the output binary number are acquired from the allocated binary digits of the input binary number, whereby an arbitrary, an i.sup.th bit digit of the output binary number is equal to the i.sup.