Patents by Inventor Mohammed Kasem
Mohammed Kasem has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10032901Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.Type: GrantFiled: April 5, 2016Date of Patent: July 24, 2018Assignee: Vishay-SiliconixInventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
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Publication number: 20170025527Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.Type: ApplicationFiled: April 5, 2016Publication date: January 26, 2017Inventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
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Patent number: 9306056Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.Type: GrantFiled: October 30, 2009Date of Patent: April 5, 2016Assignee: Vishay-SiliconixInventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
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Publication number: 20150331438Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: ApplicationFiled: July 28, 2015Publication date: November 19, 2015Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 9136060Abstract: A method of fabricating a capacitor in a semiconductor substrate. The semiconductor substrate is doped to have a low resistivity. A second electrode, insulated from a first electrode, is formed over a front side surface and connected by a metal-filled via to the back side surface. The via may be omitted and the second electrode may be in electrical contact with the substrate or may be formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor is provided by a pair of oppositely-directed diodes formed in the substrate connected in parallel with the capacitor. Capacitance is increased while maintaining a low effective series resistance. Electrodes include a plurality of fingers, which are interdigitated with the fingers of other electrode. The capacitor is fabricated in a wafer-scale process with other capacitors, where capacitors are separated from each other by a dicing technique.Type: GrantFiled: December 28, 2007Date of Patent: September 15, 2015Assignee: VISHAY-SILICONIXInventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
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Patent number: 9093359Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: GrantFiled: June 30, 2006Date of Patent: July 28, 2015Assignee: Vishay-SiliconixInventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 9040356Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.Type: GrantFiled: June 19, 2009Date of Patent: May 26, 2015Assignee: Vishay-SiliconixInventors: Mike Chang, King Owyang, Yueh-Se Ho, Mohammed Kasem, Lixiong Luo, Wei-Bing Chu
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Patent number: 8928138Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: GrantFiled: May 13, 2010Date of Patent: January 6, 2015Assignee: Vishay-SiliconixInventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 8471381Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: GrantFiled: June 30, 2006Date of Patent: June 25, 2013Assignee: Vishay-SiliconixInventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Patent number: 8324711Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.Type: GrantFiled: March 30, 2011Date of Patent: December 4, 2012Assignee: Vishay Intertechnology, Inc.Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
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Patent number: 8004063Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.Type: GrantFiled: November 16, 2006Date of Patent: August 23, 2011Assignee: Vishay Intertechnology, Inc.Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
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Publication number: 20110176247Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.Type: ApplicationFiled: March 30, 2011Publication date: July 21, 2011Applicant: VISHAY INTERTECHNOLOGY, INC.Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
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Publication number: 20110101525Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.Type: ApplicationFiled: October 30, 2009Publication date: May 5, 2011Applicant: VISHAY-SILICONIXInventors: Deva Pattanayak, King Owyang, Mohammed Kasem, Kyle Terrill, Reuven Katraro, Kuo-In Chen, Calvin Choi, Qufei Chen, Ronald Wong, Kam Hong Lui, Robert Xu
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Publication number: 20100295152Abstract: A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor.Type: ApplicationFiled: November 16, 2006Publication date: November 25, 2010Inventors: Haim Goldberger, Sik Lui, Jacek Korec, Y. Mohammed Kasem, Harianto Wong, Jack Van Den Heuvel
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Publication number: 20100219519Abstract: A complete power management system implemented in a single surface mount package. The system may be drawn to a DC to DC converter system and includes, in a leadless surface mount package, a driver/controller, a MOSFET transistor, passive components (e.g., inductor, capacitor, resistor), and optionally a diode. The MOSFET transistor may be replaced with an insulated gate bipolar transistor, IGBT in various embodiments. The system may also be a power management system, a smart power module or a motion control system. The passive components may be connected between the leadframe connections. The active components may be coupled to the leadframe using metal clip bonding techniques. In one embodiment, an exposed metal bottom may act as an effective heat sink.Type: ApplicationFiled: May 13, 2010Publication date: September 2, 2010Inventors: King Owyang, Mohammed Kasem, Yuming Bai, Frank Kuo, Sen Mao, Sam Kuo
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Publication number: 20090278179Abstract: A semiconductor package has contacts on both sides of the dice on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice expose the metal plate without extending through the metal plate. A metal layer may be formed on the front side of the dice, covering the exposed portions of the metal plate and extending to side edges of the dice. The metal layer may cover connection pads on the front side of the dice. A second set of scribe lines are made coincident with the first set. Therefore, the metal layer remains on the side edges of the dice coupling the front and the back. As a result, the package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.Type: ApplicationFiled: July 20, 2009Publication date: November 12, 2009Applicant: VISHAY-SILICONIXInventors: Felix Zandman, Y. Mohammed Kasem, Yueh Se Ho
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Publication number: 20090256246Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.Type: ApplicationFiled: June 19, 2009Publication date: October 15, 2009Applicant: VISHAY-SILICONIXInventors: Mike Chang, King Owyang, Yueh-Se Ho, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu
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Patent number: 7595547Abstract: A semiconductor package includes a leadframe which is cup-shaped and holds a semiconductor die. The leadframe is in electrical contact with a terminal on one side of the die, and the leads of the leadframe are bent in such a way that portions of the leads are coplanar with the other side of the die, which also contains one or more terminals. A plastic capsule is formed around the leadframe and die.Type: GrantFiled: June 13, 2005Date of Patent: September 29, 2009Assignee: Vishay-SiliconixInventors: Mike Chang, King Owyang, Yueh-Se Ho, Y. Mohammed Kasem, Lixiong Luo, Wei-Bing Chu
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Patent number: 7589396Abstract: A semiconductor package with contacts on both sides of the dice on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice expose the metal plate without extending through the metal plate. A metal layer may be formed on the front side of the dice, covering the exposed portions of the metal plate and extending to side edges of the dice. The metal layer may cover connection pads on the front side of the dice. A second set of scribe lines are made coincident with the first set. Therefore, the metal layer remains on the side edges of the dice coupling the front and the back. As a result, the package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.Type: GrantFiled: April 10, 2007Date of Patent: September 15, 2009Assignee: Vishay-SiliconixInventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
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Patent number: 7394150Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.Type: GrantFiled: November 23, 2004Date of Patent: July 1, 2008Assignee: Siliconix incorporatedInventors: Mohammed Kasem, King Owyang, Frank Kuo, Serge Robert Jaunay, Sen Mao, Oscar Ou, Peter Wang, Chang-Sheng Chen