Abstract: A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Abstract: A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Abstract: A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Abstract: A method of managing the configuration, design parameters, and functionality of an integrated circuit (IC) design using a hardware description language (HDL). Instructions can be added, subtracted, or generated by the designer interactively during the design process, and customized HDL descriptions of the IC design are generated through the use of scripts based on the user-edited instruction set and inputs. The customized HDL description can then be used as the basis for generating “makefiles” for purposes of simulation and/or logic level synthesis. The method further affords the ability to generate an HDL model of a complete device, such as a microprocessor or DSP. A computer program implementing the aforementioned method and a hardware system for running the computer program are also disclosed.

Abstract: Digital processor apparatus having an instruction set architecture (ISA) with instruction words of varying length. In the exemplary embodiment, the processor comprises an extended user-configurable RISC processor with four-stage pipeline (fetch, decode, and writeback) and associated logic that is adapted to decode and process both 32-execute, bit and 16-bit instruction words present in a single program, thereby increasing the flexibility of the instruction set, and allowing for greater code compression and reduced memory overhead. Free-form use of the different length instructions is provided with no required mode shift. An improved instruction aligner and code compression architecture is also disclosed.