Abstract: Static random access memory (SRAM) cells are disclosed. In one example embodiment the SRAM cell includes a latch having a first node and a second node for storing bit information at the first node and a complement of the bit at the second node. The SRAM cell further includes a first switch controlled by a write operation signal, connected between a supply voltage and a first pull-up transistor of the latch and a third switch controlled the write operation signal, connected between the second node and a ground. The SRAM cell further includes a second switch controlled by the write operation signal, connected between the supply voltage and a second pull-up transistor and a fourth switch controlled by the write operation signal, connected between the second node and the ground. The write operation signals are generated by a first complex gate and a second complex gate.