Abstract: Embodiments disclosed herein include electronics packages and methods of forming such packages. In an embodiment, the electronics package comprises a first substrate and a plurality of first conductive pads on the first substrate. In an embodiment, the electronics package further comprises a second substrate and a plurality of second conductive pads on the second substrate. In an embodiment, the electronics package further comprises a plurality of interconnects between the first and second substrate. In an embodiment, each interconnect electrically couples one of the first conductive pads to one of the second conductive pads. In an embodiment, the interconnects comprise strands of conductive material that are woven on themselves to form a mesh-like structure.

Abstract: Disclosed herein is a composite material composition for producing a biodegradable composite material. The biodegradable composite material is at least one of air resistant and water-resistant. Further, the composite material composition includes fiber present in an amount of from 30% to 50% by weight based on the total weight of the composite material composition. Further, the composite material composition includes starch present in an amount of from 20% to 40% by weight based on the total weight of the composite material composition. Further, the composite material composition includes filler particles present in an amount of from 20% to 40% by weight based on the total weight of the composite material composition and at least one binding agent present in an amount of from 1% to 5% by weight based on the total weight of the composite material composition. Further, the at least one binding agent is biodegradable.

Abstract: An exemplary method includes receiving information relating to a long bone, and generating a bone model representative of the long bone. The long bone includes a shaft, and the bone model includes a shaft model representative of at least a portion of the shaft. The method includes identifying a target orientation for the bone model, and generating a cropped model including at least a portion of the shaft model. The method further includes generating cylinder parameters based at least in part upon the cropped model, registering the cylinder to the cropped model, and generating registration information related to the registering. The method further includes generating a correction angle based upon the registration information, and generating a corrected model based upon the correction angle. The method may further include generating an adjusted model based upon the corrected model, and generating a surgical device using the adjusted model.

Abstract: Embodiments disclosed herein include electronics packages and methods of forming such packages. In an embodiment, the electronics package comprises a first substrate and a plurality of first conductive pads on the first substrate. In an embodiment, the electronics package further comprises a second substrate and a plurality of second conductive pads on the second substrate. In an embodiment, the electronics package further comprises a plurality of interconnects between the first and second substrate. In an embodiment, each interconnect electrically couples one of the first conductive pads to one of the second conductive pads. In an embodiment, the interconnects comprise strands of conductive material.

Abstract: A method according to one embodiment includes locating distal lateral and medial condyles and posterior lateral and medial condyles a femoral bone model, and determining a posterior resection plane based on locations of the distal lateral and medial condyles, one or more dimensions of a prospective femoral implant, and one or more surgical preferences. The method may further include determining a first distance between the posterior medial condyle and the posterior resection plane and a second distance between the posterior lateral condyle and the posterior resection plane, determining a difference between a target value and an average of the first distance and the second distance, wherein the target value is associated with a thickness of the prospective femoral implant, and selecting a desired femoral implant size based on the difference between the target value and the average determined for each of a plurality of possible femoral implant sizes.

Abstract: A method for efficiently determining and displaying pertinent information determined from multiple input and calculated parameters associated with a videoconference call. The method for efficiently determining and displaying this personal information is performed using input from the user at an endpoint and calculated information throughout the videoconference to present personal information, about the currently speaking person, to all participants. Videoconferencing systems are typically used by multiple people at multiple locations. The method of this disclosure allows for more user interaction and knowledge transfer amongst the participants. By sharing information between the different locations participants are more aware of who is speaking at any given time and the importance to be applied to what that particular person is saying.

Abstract: Method and circuitry for de-skewing data in data communication networks such as a SONET. The data is sent from a system chip to a framer chip where the data is de-skewed. To detect data skew, the system chip sends a training sequence to the framer chip. The information bits sent to the framer chip are searched in order to detect the training sequence. The training sequences contain clear transition patterns at which all 16 bits of the transmit data and the TCTL signal line are inverted. If any bit does not invert, this bit must be a skewed bit. Based on the data one clock cycle before and one clock cycle after this transition, the skewed bit can be corrected back. After the data skew is detected, a multiplexing logic circuitry is used to correct the skew based on one clock cycle either before or after the transition. The multiplexing logic circuitry includes at least three registers coupled to the inputs of the multiplexing logic circuitry.

Abstract: An embodiment of the present invention provides an apparatus, comprising a multilayer filter including a first resonator on a first layer of dielectric material or low-temperature-co fired-ceramic, a second resonator coupled to the first resonator on a second layer of dielectric material or low-temperature-co fired-ceramic, a third resonator coupled to the second resonator and cross coupled to the first resonator, and wherein a voltage tunable dielectric capacitor is connected to at least one of the resonators to electrically tune the multilayer filter.

Abstract: Method and circuitry for de-skewing data in data communication networks such as a SONET. The data is sent from a system chip to a framer chip where the data is de-skewed. To detect data skew, the system chip sends a training sequence to the framer chip. The information bits sent to the framer chip are searched in order to detect the training sequence. The training sequences contain clear transition patterns at which all 16 bits of the transmit data and the TCTL signal line are inverted. If any bit does not invert, this bit must be a skewed bit. Based on the data one clock cycle before and one clock cycle after this transition, the skewed bit can be corrected back. After the data skew is detected, a multiplexing logic circuitry is used to correct the skew based on one clock cycle either before or after the transition. The multiplexing logic circuitry includes at least three registers coupled to the inputs of the multiplexing logic circuitry.

Abstract: Method and circuitry for de-skewing data in data communication networks such as a SONET. The data is sent from a system chip to a framer chip where the data is de-skewed. To detect data skew, the system chip sends a training sequence to the framer chip. The information bits sent to the framer chip are searched in order to detect the training sequence. The training sequences contain clear transition patterns at which all 16 bits of the transmit data and the TCTL signal line are inverted. If any bit does not invert, this bit must be a skewed bit. Based on the data one clock cycle before and one clock cycle after this transition, the skewed bit can be corrected back. After the data skew is detected, a multiplexing logic circuitry is used to correct the skew based on one clock cycle either before or after the transition. The multiplexing logic circuitry includes at least three registers coupled to the inputs of the multiplexing logic circuitry.

Abstract: When a user of a subscriber unit (SU) originates a dispatch, or Push-to-Talk (PTT), non-local call with a target SU, a communication system serving the originating SU notifies the originating SU that the call is a non-local call before establishing the call. By notifying the originating SU as to whether the call is a non-local call, a user of the originating SU may make an informed decision as to whether to incur costs associated with a non-local dispatch or PTT call before completing the call.

Abstract: Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.

Abstract: A voltage-controlled tunable comb-ring type filter which includes a plurality of resonators and wherein the plurality of resonators include a first of at least two combline type resonators, a first of at least one ring type resonator coupled to the first of at least two combline type resonator, a second of the at least two combline type resonator coupled to the first of at least one ring type resonator and cross coupled to the first of at least two combline type resonators, and at least one of the plurality of resonators includes at least one variable capacitor. An input transmission line is connected with at least one of the plurality of resonators and an output transmission line is connected with at least one of the resonators;.

Abstract: Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.

Abstract: Method and circuitry for de-skewing data in data communication networks such as a SONET. The data is sent from a system chip to a framer chip where the data is de-skewed. To detect data skew, the system chip sends a training sequence to the framer chip. The information bits sent to the framer chip are searched in order to detect the training sequence. The training sequences contain clear transition patterns at which all 16 bits of the transmit data and the TCTL signal line are inverted. If any bit does not invert, this bit must be a skewed bit. Based on the data one clock cycle before and one clock cycle after this transition, the skewed bit can be corrected back. After the data skew is detected, a multiplexing logic circuitry is used to correct the skew based on one clock cycle either before or after the transition. The multiplexing logic circuitry includes at least three registers coupled to the inputs of the multiplexing logic circuitry.

Abstract: A multiprocessor computer system comprises a plurality of network interfaces each adapted to be coupled to respective external networks for receiving and sending data packets to and from remote devices coupled to the external networks via a particular communication protocol. The multiprocessor computer system further comprises a plurality of symmetrical processors including a control processor and at least one switching processor. The switching processor further includes at least one network application executing thereon. The control processor further includes an operating system portion having a kernel memory and at least one network driver communicating with the plurality of network interfaces. A buffer descriptor list is accessible by the network application and the network driver.

Abstract: A data packet switching system comprises a plurality of network interfaces each adapted to be coupled to respective external networks for receiving and sending data packets to and from the external networks via a particular communication protocol. The data packet switching system further includes a plurality of symmetrical processors, including a first processor providing a control processor and remaining ones of the processors each providing data packet switching processors. The data packet switching processors are coupled to the plurality of network interfaces. The control processor further includes a user portion and an operating system portion. The operating system portion is provided with a pseudo-network driver that appears to be a network interface to user application programs operating on the user portion of the control processor. A memory space is shared by the control processor and the data packet switching processors.

Abstract: A processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem. The processor interface chip includes logic for interfacing between the microprocessors and a main memory, logic for pipelining multiple microprocessor requests between the microprocessors and main memory, logic for prefetching data before a microprocessor issues a read request, logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors' fixed memory location for boot code, and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip.

Abstract: A data packet switching system comprises a plurality of network interfaces each adapted to be coupled to respective external networks for receiving and sending data packets to and from the external networks via a particular communication protocol. The data packet switching system further includes a plurality of symmetrical processors, including a first processor providing a control processor and remaining ones of said processors each providing data packet switching processors. The control processor is coupled to a corresponding one of the plurality of network interfaces and the data packet switching processors are coupled to each remaining one of the plurality of network interfaces. A switch is coupled to the control processor through the corresponding one of the network interfaces and is coupled to at least one of the switching processors through at least one other one of the network interfaces.

Abstract: Method and apparatus for processing data packets within a communication system such as a synchronous optical network (SONET) detect an invalid byte and drop and shift bytes of data to address an invalid byte. A method according to one embodiment of the present invention, includes receiving a first data packet in the communication system. Thereafter, it is determined whether this packet ends with both a valid byte and an invalid byte of data. If both the valid and invalid bytes are present, the invalid byte is dropped and a valid byte from a succeeding data packet is concatenated with the valid byte of the first data packet, and byte shifting occurs in the succeeding data packet. Byte shifting continues until a second packet ending with an invalid byte is encountered. Skipping a clock cycle at the end of the second packet with the invalid byte results in packets with only valid data.