Abstract: In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.

Abstract: Methods and apparatus are provided for decision-feedback equalization with global minimum convergence. A threshold position of one or more DFE latches employed by a decision-feedback equalizer is determined by obtaining a plurality of samples of a single-sided data eye using at least one decision latch and at least one roaming latch; comparing the samples obtained by the at least one decision latch and at least one roaming latch to identify an upper and lower voltage boundary of the single-sided data eye; and determining a threshold position of the one or more DFE latches based on the upper and lower voltage boundaries. The comparison can optionally comprise obtaining an exclusive or (XOR) of the samples obtained by the at least one decision latch and at least one roaming latch. The XOR comparison positions an opening for the single-sided data eye at a zero hit count.

Abstract: A method and apparatus is presented for establishing an equivalence between the Hamming branch metric scheme and the Manhattan branch metric scheme. A signal format converter is presented to convert input signal in a first number system such as binary or two's complement, into a second number system. The signal format converter implemented at the input to a Viterbi decoder allows the use of a Viterbi decoder designed for a Manhattan metric sceme in an application where the signals are represented in two's complement. Similarly a Viterbi decoder designed for a Hamming metric scheme can be implemented in an application where the signals are represented in unsigned binary. The signal format converter can be used with both a hard decision Viterbi decoder and a soft decision Viterbi decoder.

Abstract: A method and apparatus for obtaining a soft symbol decoded output of a received signal by a two pass Viterbi operation. The technique is especially advantageous where the signal is convolutionally encoded with large constraint lengths. During the first pass, the error-correction co-processor (ECCP) is programmed for hard decoded output alone. After all the received symbol sets are hard-bit decoded, a second pass Viterbi operation is performed. Using the previously decoded hard bit to identify the most likely next state at an initial time instant, and initializing the present states at that initial time instant with pre-saved accumulated costs from the first pass Viterbi operation, branch metrics are computed for those state transitions leading to the most likely next state at that time instant.