Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, an external memory interface configured to couple the on-chip memory with an external memory providing a backing store to the on-chip memory, and bandwidth monitor configured to measure a bandwidth utilization of the external memory. The network processor also includes a processor configured to apply the bandwidth utilization of the external memory to a congestion notification profile, to generate one or more congestion notifications based on the bandwidth utilization applied to the congestion notification profile, and to send the one or more congestion notifications to the source device to request decreasing packet rate for decreasing the bandwidth utilization of the external memory.

Abstract: Systems and methods for flowlet switching using memory instructions. One embodiment is a method of distributing packets over multiple paths. The method includes determining an elapsed time between a packet and a previous packet. The method further includes, in response to determining that the elapsed time is less than an inter-packet gap threshold: retaining a previously selected path value indicated in the flow record, and providing the previously selected path value to the processing thread for transmitting the packet over a previously selected path associated with the previous packet. The method also further includes, in response to determining that the elapsed time is greater than the inter-packet gap threshold: updating the flow record by replacing the previously selected path value with the path value of the selected path of the memory instruction, and providing the path value to the processing thread for transmitting the packet over the selected path.

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, and external memory configured to provide a backing store to the on-chip memory. The network processor also includes a processor configured, in response to determining that the source device is unresponsive to a congestion notification, to reduce a size of one or more queues to prevent packets transferring from the on-chip memory to the external memory.

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, and external memory configured to provide a backing store to the on-chip memory. The network processor also includes a processor configured, in response to determining that the source device is unresponsive to a congestion notification, to reduce a size of one or more queues to prevent packets transferring from the on-chip memory to the external memory.

Abstract: Systems and methods for flowlet switching using memory instructions. One embodiment is a method of distributing packets over multiple paths. The method includes determining an elapsed time between a packet and a previous packet. The method further includes, in response to determining that the elapsed time is less than an inter-packet gap threshold: retaining a previously selected path value indicated in the flow record, and providing the previously selected path value to the processing thread for transmitting the packet over a previously selected path associated with the previous packet. The method also further includes, in response to determining that the elapsed time is greater than the inter-packet gap threshold: updating the flow record by replacing the previously selected path value with the path value of the selected path of the memory instruction, and providing the path value to the processing thread for transmitting the packet over the selected path.

Abstract: Systems and methods for protecting external memory resources to prevent bandwidth collapse in a network processor. One embodiment is a network processor including an input port configured to receive packets from a source device, on-chip memory configured to store packets in queues, an external memory interface configured to couple the on-chip memory with an external memory providing a backing store to the on-chip memory, and bandwidth monitor configured to measure a bandwidth utilization of the external memory. The network processor also includes a processor configured to apply the bandwidth utilization of the external memory to a congestion notification profile, to generate one or more congestion notifications based on the bandwidth utilization applied to the congestion notification profile, and to send the one or more congestion notifications to the source device to request decreasing packet rate for decreasing the bandwidth utilization of the external memory.

Abstract: Disclosed are systems and methods for scaling Massively Scalable Data Center (MSDC) networks with a large number of end-point tunnels utilizing Equal-cost multi-path routing (ECMP). The systems and methods can use the NO-OP label operations to maintain single ECMP objects to switch a set of segment routing tunnels that share the same ECMP links. The forwarding engine can determine the use of the NO-OP label operation and update a received packet to enable the use of the single ECMP objects of the set of segment routing tunnels.

Abstract: Disclosed are systems and methods for scaling Massively Scalable Data Center (MSDC) networks with a large number of end-point tunnels utilizing Equal-cost multi-path routing (ECMP). The systems and methods can use the NO-OP label operations to maintain single ECMP objects to switch a set of segment routing tunnels that share the same ECMP links. The forwarding engine can determine the use of the NO-OP label operation and update a received packet to enable the use of the single ECMP objects of the set of segment routing tunnels.

Abstract: Disclosed are systems and methods for scaling Massively Scalable Data Center (MSDC) networks with a large number of end-point tunnels utilizing Equal-cost multi-path routing (ECMP). The systems and methods can use the NO-OP label operations to maintain single ECMP objects to switch a set of segment routing tunnels that share the same ECMP links. The forwarding engine can determine the use of the NO-OP label operation and update a received packet to enable the use of the single ECMP objects of the set of segment routing tunnels.

Abstract: A method performed by a first network device for applying Quality-of-Service (QoS) on a virtual interface over a multi-path transport topology. The method includes receiving a packet of the virtual interface from a service home network processing unit (NPU), where the virtual interface has been provisioned with a virtual interface QoS, where the service home NPU has applied the virtual interface QoS on the packet, and where the packet includes a physical transport link identifier (ID) that identifies a physical transport link over which the packet is to be forwarded. The method further includes selecting a virtual adjacency based on metadata included in the packet and using the selected virtual adjacency to select a queue based on the physical transport link ID and store the packet in the selected queue. The method further includes performing scheduling to select the queue and sending the packet over the physical transport link.

Abstract: Disclosed are systems and methods for scaling Massively Scalable Data Center (MSDC) networks with a large number of end-point tunnels utilizing Equal-cost multi-path routing (ECMP). The systems and methods can use the NO-OP label operations to maintain single ECMP objects to switch a set of segment routing tunnels that share the same ECMP links. The forwarding engine can determine the use of the NO-OP label operation and update a received packet to enable the use of the single ECMP objects of the set of segment routing tunnels.

Abstract: A method performed by a first network device for applying Quality-of-Service (QoS) on a virtual interface over a multi-path transport topology. The method includes receiving a packet of the virtual interface from a service home network processing unit (NPU), where the virtual interface has been provisioned with a virtual interface QoS, where the service home NPU has applied the virtual interface QoS on the packet, and where the packet includes a physical transport link identifier (ID) that identifies a physical transport link over which the packet is to be forwarded. The method further includes selecting a virtual adjacency based on metadata included in the packet and using the selected virtual adjacency to select a queue based on the physical transport link ID and store the packet in the selected queue. The method further includes performing scheduling to select the queue and sending the packet over the physical transport link.

Abstract: Exemplary methods receiving a packet of a virtual interface provisioned with a virtual interface QoS, wherein the virtual interface comprises a hierarchy of sub interfaces. The methods include selecting a virtual adjacency from a plurality of virtual adjacencies, wherein each virtual adjacency is associated with the virtual interface or a sub interface of the virtual interface. The methods include using the selected virtual adjacency to select a queue based on a priority of the packet, and store the packet in the selected queue. The methods include performing hierarchical scheduling based on the virtual interface QoS to select the queue from all sets of virtual interface queues of all virtual adjacencies, and sending the packet from the selected queue and a transport link identifier (ID) to a physical network processing unit.

Abstract: Exemplary methods receiving a packet of a virtual interface provisioned with a virtual interface QoS, wherein the virtual interface comprises a hierarchy of sub interfaces. The methods include selecting a virtual adjacency from a plurality of virtual adjacencies, wherein each virtual adjacency is associated with the virtual interface or a sub interface of the virtual interface. The methods include using the selected virtual adjacency to select a queue based on a priority of the packet, and store the packet in the selected queue. The methods include performing hierarchical scheduling based on the virtual interface QoS to select the queue from all sets of virtual interface queues of all virtual adjacencies, and sending the packet from the selected queue and a transport link identifier (ID) to a physical network processing unit.

Abstract: The present invention provides for adaptive filters that have improved computational and memory bandwidth proprieties. When applied to telecommunication applications, the present invention additionally provides for improved methods and systems of canceling echoes. In one embodiment of the adaptive filter of the present invention, a filter, preferably an adaptive finite impulse response (FIR) filter, of an appropriate length, N, is chosen. Once the filter is chosen, convergence is achieved and the filter is converted to an infinite impulse response (IIR) filter. In the course of operation, data is received from an input source and used to adapt the zeroes of the IIR filter using the least means square (LMS) approach, keeping the poles fixed. The adaptation process generates a set of converged filter coefficients that are then applied to the input signal to create a modified signal used to filter the data.

Abstract: The present invention is a system on chip architecture having scalable, distributed processing and memory capabilities through a plurality of processing layers. In a preferred embodiment, a distributed processing layer processor comprises a plurality of processing layers, a processing layer controller, and a central direct memory access controller. The processing layer controller manages the scheduling of tasks and distribution of processing tasks to each processing layer. Within each processing layer, a plurality of pipelined processing units (PUs), specially designed for conducting a defined set of processing tasks, are in communication with a plurality of program memories and data memories. One application of the present invention is in a media gateway that is designed to enable the communication of media across circuit switched and packet switched networks.

Abstract: The present invention provides for an improved video compression and encoding that optimizes and enhances the overall speed and efficiency of processing video data. In one embodiment, the video codec transmits the output of an entropy decoder to a lossless compressor and memory before going through inverse discrete cosine transformation and motion compensation blocks.