Abstract: A system on chip (SOC) includes a power distribution network (PDN) that has two different types of power multiplexers. The first power multiplexer type includes a lower resistance switching logic, and the second type includes a higher resistance switching logic as well as digital logic to provide an enable signal to the first type of power multiplexer. A given first-type power multiplexer may have multiple power multiplexers of the second type in a loop, the loop including communication paths for the enable signal and feeding the enable signal back to an enable input of the first-type power multiplexer.

Abstract: Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I/O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices.

Abstract: Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL) (FS-BEOL) input/output (I/O) routing and back side (BS)) BEOL (BS-BEOL) power routing for current flow organization, and related IC packages and methods of fabricating are disclosed. The IC includes a FS-BEOL metallization structure disposed on a first side of a semiconductor layer and a BS-BEOL metallization structure disposed on a second side of the semiconductor layer. The FS-BEOL metallization structure is configured to route I/O signals to the semiconductor devices. The FS-BEOL metallization structure of the IC is also configured to receive power signals to be routed to the semiconductor devices.

Abstract: Aspects of the disclosure are directed to a metal only cell-based power grid (PG) architecture. In accordance with one aspect, the power gird (PG) architecture includes a cell building block structure with a N×M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first direction and the second direction are orthogonal to one another; and a plurality of power grid (PG) cells, wherein each of the N cell building blocks and each of the M cell building blocks are occupied by a PG cell of the plurality of PG cells.

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.

Abstract: Aspects of the disclosure are directed to a metal only cell-based power grid (PG) architecture. In accordance with one aspect, the power gird (PG) architecture includes a cell building block structure with a N×M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first direction and the second direction are orthogonal to one another; and a plurality of power grid (PG) cells, wherein each of the N cell building blocks and each of the M cell building blocks are occupied by a PG cell of the plurality of PG cells.

Abstract: In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided. The MOS device may include a first set of cells adjacent to each other in a first direction. The MOS device may include a second set of cells adjacent to each other in the first direction and adjacent to the first set of cells in a second direction. The second set of cells each may include a first n-well, a second n-well, and a third n-well separated from each other. The MOS device may include an interconnect extending in the first direction in the second set of cells. The interconnect may provide a voltage source to the first n-well of each of the second set of cells.