Abstract: A processor is responsive to a thermistor temperature Tth adjacent a FET functioning as a switch to control power to a load (L) and responsive to drain-to-source voltage (VDS) of the FET. The processor stores the characteristics of the FET and a thermal model of the system hardware and uses a first set of equations to determine the temperature TJ at the junction of the FET in a stable region of operation where TJ?Tth is nearly constant. The processor is further responsive to a step change in successive measurements of VDS indicative of a lag of Tth relative to TJ thereby rendering Tth unusable in the first set of equations and immediately determines an initial FET current IFET. The processor then resolves TJ based upon a second set of equations comprising TJ=Tth+?TSS(1?e?t/?) when ?TSS+Tth?TJ and TJ=Tth+?TSS(e?t/?) when ?TSS+Tth?TJ where ? is a constant and ?TSS is the steady-state temperature difference between the TJ and Tth at the initial FET current IFET determined in accordance with ?TSS=IFET2RDS?J?th.