Abstract: A memory processing unit can be configured to compute partial products between one or more elements of a first matrix stored in a first storage location and sequential bits of one or more elements of a second matrix stored in a second storage location. The partial products can be calculated utilizing zero bit skipping to increase throughput and or reduce energy consumption. The partial products for each column of elements can be accumulated and bit shifted to compute the dot product of the first and second matrix.

Abstract: A memory processing unit can be configured to compute partial products between one or more elements of a first matrix stored in a given row of a memory cell array and sequential bits of one or more elements of a second matrix. The partial products can be calculated first sequentially across the set of rows and second sequentially across the bit positions of the elements of the second matrix. Alternatively, the partial products can be calculated first sequentially across the bit positions of the elements of the second matrix first and second sequentially across the set of rows. The partial products for each column of elements can be accumulated and bit shifted to compute the dot product of the first and second matrix.

Abstract: An in-memory computing system for computing vector-matrix multiplications includes an array of resistive memory devices arranged in columns and rows, such that resistive memory devices in each row of the array are interconnected by a respective wordline and resistive memory devices in each column of the array are interconnected by a respective bitline. The in-memory computing system also includes an interface circuit electrically coupled to each bitline of the array of resistive memory devices and computes the vector-matrix multiplication between an input vector applied to a given set of wordlines and data values stored in the array. For each bitline, the interface circuit receives an output in response to the input being applied to the given wordline, compares the output to a threshold, and increments a count maintained for each bitline when the output exceeds the threshold. The count for a given bitline represents a dot-product.

Abstract: For decades, advances in electronics were directly related to the scaling of CMOS transistors according to Moore's law. However, both the CMOS scaling and the classical computer architecture are approaching fundamental and practical limits. A novel memory-centric, reconfigurable, general purpose computing platform is proposed to handle the explosive amount of data in a fast and energy-efficient manner. The proposed computing architecture is based on a single physical resistive memory-centric fabric that can be optimally reconfigured and utilized to perform different computing and data storage tasks in a massively parallel approach. The system can be tailored to achieve maximal energy efficiency based on the data flow by dynamically allocating the basic computing fabric to storage, arithmetic, and analog computing including neuromorphic computing tasks.

Abstract: For decades, advances in electronics were directly related to the scaling of CMOS transistors according to Moore's law. However, both the CMOS scaling and the classical computer architecture are approaching fundamental and practical limits. A novel memory-centric, reconfigurable, general purpose computing platform is proposed to handle the explosive amount of data in a fast and energy-efficient manner. The proposed computing architecture is based on a single physical resistive memory-centric fabric that can be optimally reconfigured and utilized to perform different computing and data storage tasks in a massively parallel approach. The system can be tailored to achieve maximal energy efficiency based on the data flow by dynamically allocating the basic computing fabric to storage, arithmetic, and analog computing including neuromorphic computing tasks.