Patents by Inventor Mohan Dunga

Mohan Dunga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10984876
    Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: April 20, 2021
    Assignee: SanDiskTechnologies LLC
    Inventors: Piyush Dak, Mohan Dunga, Chao Qin, Muhammad Masuduzzaman, Xiang Yang
  • Patent number: 10978145
    Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: April 13, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Biswajit Ray, Peter Rabkin, Mohan Dunga, Gerrit Jan Hemink, Changyuan Chen
  • Patent number: 10971240
    Abstract: The storage device comprises a non-volatile memory coupled to a controller. The controller is configured to determine a first programming voltage by performing at least one program-verify iteration on a first word line using a voltage value which starts as a predetermined first initial voltage and is sequentially increased by a first voltage step amount following each failure to successfully program until the programming is completed. The controller is also configured to determine a second initial programming voltage by decreasing the first programming voltage by a second voltage step amount. The controller is further configured to perform at least one program-verify iteration on a second word line of the plurality of word lines using a voltage value which starts as the second initial programming voltage and is increased by the first voltage step amount following each sequential failure to successfully program until the programming is completed.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: April 6, 2021
    Inventors: Mohan Dunga, Pitamber Shukla
  • Publication number: 20210050054
    Abstract: Apparatuses and techniques are provided for programming memory cells while reducing widening of a threshold voltage distribution due to changes in the temperature between the time of programming and the time of a subsequent read operation. One technique is based on a correlation between program speed and temperature coefficient (Tco). A different verify test is used for different memory cells which have a common assigned data state according to the program loop number and the temperature. Another technique is based on sensing the memory cells to measure their subthreshold slope and classifying the memory cells into groups. The sensing can occur as a separate operation before programming or as part of the programming of user data. The subsequent programming of the memory cells involves adjusting the verify test of each memory cell based on its group and the temperature.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 18, 2021
    Applicant: SanDisk Technologies LLC
    Inventors: Biswajit Ray, Peter Rabkin, Mohan Dunga, Gerrit Jan Hemink, Changyuan Chen
  • Patent number: 10878926
    Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: December 29, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Pitamber Shukla, Mohan Dunga, Anubhav Khandelwal
  • Publication number: 20200402594
    Abstract: Various methods include receiving, by a controller, a temperature reading of a memory array, the temperature reading includes a temperature value; determining the temperature value is below a first threshold; in response, modifying a duration of a verify cycle of a write operation to create a modified verify cycle; then programming a first data into the memory array using the write operation that uses the modified verify cycle. Methods additionally include receiving a second temperature reading of the memory array, the second temperature reading includes a second temperature value; determining the second temperature value is below a second threshold, in response, decreasing the duration of a verify cycle of a verify cycle to create a second verify cycle, where the second verify cycle is shorter than the modified verify cycle; and then programming a second data into the memory array using the write operation that uses the second verify cycle.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Applicant: SanDisk Technologies LLC
    Inventors: Piyush Dak, Mohan Dunga, Chao Qin, Muhammad Masuduzzaman, Xiang Yang
  • Patent number: 10847452
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: November 24, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Luisa Lin, Mohan Dunga, Venkatesh P. Ramachandra, Peter Rabkin, Masaaki Higashitani
  • Patent number: 10825827
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: November 3, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mohan Dunga, James Kai, Venkatesh P. Ramachandra, Piyush Dak, Luisa Lin, Masaaki Higashitani
  • Patent number: 10818685
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and an I/O interface. A portion of the memory die is used as a pool capacitor for the I/O interface.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: October 27, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mohan Dunga, James Kai, Venkatesh P. Ramachandra, Piyush Dak, Luisa Lin, Masaaki Higashitani
  • Patent number: 10789992
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the I/O pads.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: September 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Luisa Lin, Mohan Dunga, Venkatesh P. Ramachandra, Peter Rabkin, Masaaki Higashitani
  • Patent number: 10790031
    Abstract: A data storage system performs operations including receiving a data read command corresponding to a first memory cell; determining whether the first memory cell is in a first read condition; if the first memory cell is in the first read condition: applying a first voltage level to the first memory cell, the first voltage level being a predetermined voltage level corresponding to a read operation for memory cells in the first read condition; and sensing a first level of current, or lack thereof, through the first memory cell during application of the first voltage level to the first memory cell; and if the first memory cell is not in the first read condition: applying a second voltage level to the first memory cell, the second voltage level being a voltage level corresponding to a read operation for memory cells in a read condition other than the first read condition.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: September 29, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Piyush Sagdeo, Chris Yip, Sourabh Sankule, Pitamber Shukla, Anubhav Khandelwal, Mohan Dunga, Niles Yang
  • Publication number: 20200294909
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Luisa Lin, Mohan Dunga, Venkatesh P. Ramachandra, Peter Rabkin, Masaaki Higashitani
  • Publication number: 20200294910
    Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Luisa Lin, Mohan Dunga, Venkatesh P. Ramachandra, Peter Rabkin, Masaaki Higashitani
  • Patent number: 10755798
    Abstract: Recovering data from a faulty memory block in a memory system. Various methods include: reading a target word line in a memory block to obtain a first data; determining the first data has an uncorrectable error; and then adjust bias parameters of a first group of neighboring word lines within the memory block, where adjusting bias parameters creates a first adjusted bias parameters; and reading the target word line using the adjusted bias parameters to obtain second data from the target word line. The method also includes determining the second data has a second uncorrectable error; and then adjusting bias parameters of a second group of lines within the memory block, where adjusting the bias parameters of the second group creates second adjusted bias parameters; and reading the target word line using the first and second adjusted bias parameters to obtain a third data from the target word line.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: August 25, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Niles Yang, Pitamber Shukla, Mohan Dunga
  • Patent number: 10714169
    Abstract: A non-volatile memory system and corresponding method of operation are provided. The system includes non-volatile memory cells, each retaining a threshold voltage within a threshold window. The non-volatile memory cells include multi-bit cells each configured to store a plurality of bits of data with the threshold window partitioned into bands each having a band width. The bands include a lowest band denoting an erased state and increasing bands. A control circuit programs a first set of the data into the multi-bit cells in a single-bit mode using first target states being one of the erased state and a tight intermediate state having a distribution of the threshold voltage no wider than the band width of one of the increasing bands. The control circuit also programs a second set of the data into the multi-bit cells in a multi-bit mode with each of the multi-bit cells storing the plurality of bits.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: July 14, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Phil Reusswig, Pitamber Shukla, Sarath Puthenthermadam, Mohan Dunga, Sahil Sharma, Rohit Sehgal, Niles Yang
  • Publication number: 20200203365
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, where each of the memory stack structures contains a respective memory film and a respective vertical semiconductor channel, drain regions contacting an upper end of a respective one of the vertical semiconductor channels, first contact via structures directly contacting a first subset of the drain regions and each having a first horizontal cross-sectional area, and second contact via structures directly contacting a second subset of the drain regions and each having a second horizontal cross-sectional area that is greater than the first horizontal cross-sectional area.
    Type: Application
    Filed: December 24, 2018
    Publication date: June 25, 2020
    Inventors: Lishan WENG, Fumiaki TOYAMA, Mohan DUNGA
  • Publication number: 20200194094
    Abstract: Recovering data from a faulty memory block in a memory system. Various methods include: reading a target word line in a memory block to obtain a first data; determining the first data has an uncorrectable error; and then adjust bias parameters of a first group of neighboring word lines within the memory block, where adjusting bias parameters creates a first adjusted bias parameters; and reading the target word line using the adjusted bias parameters to obtain second data from the target word line. The method also includes determining the second data has a second uncorrectable error; and then adjusting bias parameters of a second group of lines within the memory block, where adjusting the bias parameters of the second group creates second adjusted bias parameters; and reading the target word line using the first and second adjusted bias parameters to obtain a third data from the target word line.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Niles Yang, Pitamber Shukla, Mohan Dunga
  • Patent number: 10643695
    Abstract: A sense amplifier for a memory circuit that can sense into the deep negative voltage threshold region is described. A selected memory cell is sensed by discharging a source line through the memory cell into the bit line and sense amplifier. While discharging the source line through the memory cell into the sense amplifier, a voltage level on the discharge path is used to set the conductivity of a discharge transistor to a level corresponding to the conductivity of the selected memory cell. A sense node is then discharged through the discharge transistor. By allowing the sense amplifier to bias a memory cell being sensed to a selected one of multiple bias levels during a sensing operation, multiple target data states can be concurrently program verified, leading to higher performance when writing data.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: May 5, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Hao Nguyen, Chia-kai Chou, Mohan Dunga
  • Patent number: 10559370
    Abstract: A circuit includes a detection circuit configured to determine a capacitance delay (RC-delay) in an initial stage of a read or program operation and to adjust timing for detecting data in a subsequent stage, or portion of a stage, of the same read or programming operation. In particular, during a program operation a detection circuit may be configured to detect a pre-charge time for a bit line and adjust a timing of subsequent verify stages of the bit line during the same program operation based on the detected pre-charge time. Additionally, a word line circuit may be configured to detect a pre-charge time for a word line during an initial stage of a read operation and adjust read timing for a subsequent portion of the same read stage, or subsequent read stage of the read operation based on the detected word line pre-charge time.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: February 11, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Xiang Yang, Piyush Dak, Wei Zhao, Huai-Yuan Tseng, Deepanshu Dutta, Mohan Dunga
  • Publication number: 20200035313
    Abstract: A high-performance write operation to program data to a group of non-volatile memory cells may be completed in response to applying a single programming pulse to the group. Programming of the cells may be verified (and/or corrected) after completion of the command. Verifying programming of the cells may comprise identifying under-programmed cells, and applying an additional programming pulse to the identified cells. The under-programmed cells may comprise cells within an under-program range below a target level. The under-program range may be determined based on a threshold voltage distribution of the cells in response to applying the single programming pulse.
    Type: Application
    Filed: October 2, 2019
    Publication date: January 30, 2020
    Inventors: Pitamber Shukla, Mohan Dunga, Anubhav Khandelwal