Patents by Inventor Mohan Govindaraj

Mohan Govindaraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11347702
    Abstract: Examples described herein relate to migrating data in a system having multi-tiered physical storage. In an example, relative weights corresponding to a plurality of data access parameters may be determined based on a ranking associated with each of the plurality of data access parameters. Further, a priority metric corresponding to each of a plurality of candidate types may be determined based on the relative weights of the plurality of data access parameters. Furthermore, one or more candidate types may be selected from the plurality of candidate types based on the priority metric corresponding to each of the plurality of candidate types. Moreover, data containers corresponding to the selected one or more candidate types may be migrated from a first tier storage to a second tier storage.
    Type: Grant
    Filed: October 17, 2020
    Date of Patent: May 31, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Mohan Govindaraj, Ashutosh Kumar, V. V. Satyanarayana Reddy N, Rachit Gupta
  • Publication number: 20210365416
    Abstract: Aspects pertaining to a distributed file system are described. In an example, system call is made by a server computing device on receiving a request for accessing a file, by a client device operating on a first computing architecture. A mount parameter is received in response to the system calls, wherein the mount parameter is to prescribe a computing architecture of a computing device to access the file system. Attribute information pertaining to the file to be accessed may thus be modified on determining the mount parameter to prescribe a first computing architecture for the client device, wherein modified attribute information is of a bit-size conforming to the first computing architecture.
    Type: Application
    Filed: April 20, 2021
    Publication date: November 25, 2021
    Inventors: Ravikumar Chilaka, Mohan Govindaraj
  • Publication number: 20210191910
    Abstract: Examples described herein relate to migrating data in a system having multi-tiered physical storage. In an example, relative weights corresponding to a plurality of data access parameters may be determined based on a ranking associated with each of the plurality of data access parameters. Further, a priority metric corresponding to each of a plurality of candidate types may be determined based on the relative weights of the plurality of data access parameters. Furthermore, one or more candidate types may be selected from the plurality of candidate types based on the priority metric corresponding to each of the plurality of candidate types. Moreover, data containers corresponding to the selected one or more candidate types may be migrated from a first tier storage to a second tier storage.
    Type: Application
    Filed: October 17, 2020
    Publication date: June 24, 2021
    Inventors: Mohan Govindaraj, Ashutosh Kumar, V. V. Satyanarayana Reddy N, Rachit Gupta
  • Publication number: 20070033561
    Abstract: One embodiment of the present invention provides a system that speeds up timing analysis by reusing delays computed for isomorphic subcircuit. During operation, the system receives a circuit block to be analyzed, wherein the circuit block is in the form of a netlist. The system then subdivides the circuit block into a set of subcircuits. The subcircuits are then partitioned into equivalence classes, which contain subcircuits which are topologically isomorphic to each other. Next, the system performs a timing analysis by tracing paths through a timing graph for the circuit block. During this timing analysis, whenever a delay is required for a subcircuit, the system determines if a corresponding delay has been already computed for the equivalence class associated with the subcircuit. If so, the system reuses the delay. If not, the system computes the delay for the subcircuit, and then associates the computed delay with the equivalence class so that the computed delay can be reused for isomorphic subcircuits.
    Type: Application
    Filed: August 4, 2005
    Publication date: February 8, 2007
    Inventors: Larry Jones, Feng Li, Mohan Govindaraj, Bradley Roetcisoender, Michael Weaver