Abstract: Systems, methods, and other embodiments associated with random number generators are described. One system embodiment includes a random number generator logic that may produce an initial random number from a first set of three inputs. The system embodiment may receive the three inputs from sources including an internal counter entropy source (ICES), an internal arbitrary entropy source (IAES), and an external entropy source (EES). The system embodiment may generate a first random number from a first set of three inputs (e.g., value from ICES, value from IAES, value from EES) but may then generate subsequent random numbers from a different set of three inputs (e.g., value from ICES, value from IAES, previous random number).

Abstract: The present invention provides a system, method and apparatus for asynchronous communication in wireless sensor networks. Each sensor includes a transmitter normally operating in a sleep mode, a low power receiver having a memory, a sensing module, and a processor normally operating in a sleep mode communicably coupled to the transmitter, the low power receiver and the sensing module. Data is received via the low power receiver and stored in the memory. Whenever a wakeup time occurs, the transmitter and the processor are put in an operational mode, sensory data is obtained from the sensing module, the sensory data is processed, the received data is obtained from the low power receiver memory, the processed sensory data and the received data are transmitted via the transmitter, and the transmitter and the processor are put in the sleep mode.

Abstract: An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a hot-plug reset, of one or more processors. The enumeration is provided to a system architecture operating system in which a compute node is hot-plugged. Once enumeration is complete, the compute node is started in response to an operating system activation request. Accordingly, once device enumeration, as well as resource enumeration are complete, the one or more processors of the processor memory node are activated, such that the operating system may begin utilizing the processors of the hot-plugged compute node.

Abstract: In a method for switching to a spare memory module during runtime, a processing system determines that utilization of an active memory module in the processing system should be discontinued. The processing system may then activate a mirror copy mode that causes a memory controller in the processing system to copy data from the active memory module to the spare memory module when the data is accessed in the active memory module. An operating system (OS) in the processing system may then access data in the active memory module to cause the memory controller to copy data from the active memory module to the spare memory module. The processing system may then reconfigure the memory controller to direct reads and writes to the spare memory module instead of the active memory module. Other embodiments are described and claimed.

Abstract: In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.

Abstract: In some embodiments a boot progress of a System Boot Strap Processor in a multi-processor system is monitored and a boot processor failure is detected using an Application Processor. If the boot processor failure is detected at least a portion of the system is reinitialized (and/or the system is rebooted). Other embodiments are described and claimed.

Abstract: Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, wherein the link status is based at least in part on the result from the link training and the result from the BIST.

Abstract: When a processing system boots, it may retrieve an encrypted version of a cryptographic key from nonvolatile memory to a processing unit, which may decrypt the cryptographic key. The processing system may also retrieve a predetermined authentication code for software of the processing system, and the processing system may use the cryptographic key to compute a current authentication code for the software. The processing system may then determine whether the software should be trusted, by comparing the predetermined authentication code with the current authentication code. In various embodiments, the processing unit may use a key stored in nonvolatile storage of the processing unit to decrypt the encrypted version of the cryptographic key, a hashed message authentication code (HMAC) may be used as the authentication code, and/or the software to be authenticated may be boot firmware, a virtual machine monitor (VMM), or other software. Other embodiments are described and claimed.

Abstract: An augmented boot code module includes instructions to be executed by a processing unit during a boot process. The augmented boot code module also includes an encrypted version of a cryptographic key that can be decrypted with a cryptographic key that remains in the processing unit despite a reset of the processing unit. In one embodiment, the processing unit may decrypt the encrypted version of the cryptographic key and then use the decrypted key to establish a protected communication channel with a security processor, such as a trusted platform module (TPM). Other embodiments are described and claimed.

Abstract: Apparatuses, methods, and systems for reconfiguring a secure system are disclosed. In one embodiment, an apparatus includes a configuration storage location, a lock, and lock override logic. The configuration storage location is to store information to configure the apparatus. The lock is to prevent writes to the configuration storage location. The lock override logic is to allow instructions executed from sub-operating mode code to override the lock.

Abstract: In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.

Abstract: Embodiments include systems and methods for processing Reliability, Availability and Serviceability (RAS) events in a computer system. Embodiments comprise processing critical events in a first portion of a Management Interrupt (MI) period. The MI period is chosen to be not greater than a maximum tolerable Operating System (OS) latency period. If time remains in a current MI period after processing critical events, the system then processes non-critical events during the time remaining in the current MI period. If at the end of the current MI period, some non-critical events remain to be processed, a subsequent MI period is scheduled to process the remaining non-critical events.

Abstract: Methods and apparatus for initiating secure operations in a microprocessor system are described. In one embodiment, a system includes a processor to execute a secured enter instruction, and a chipset to cause the system to enter a quiescent state during execution of the secured enter instruction.

Abstract: An embodiment of the present invention relates generally to computer configuration and, more specifically, to a system and method to seamlessly determine the component configurations of a series of heterogeneous platforms and enable their respective component configurations to be intelligently migrated from one platform to another. In some embodiments, the invention involves generating configuration binaries for a plurality of target platforms. The configuration binaries are used with tools to create configuration directives for the target machines. In at least one embodiment, the configuration directives are sent to the target platforms in a scripting language. In some embodiments, the scripts are automatically generated by a tool using the configuration binaries for various platforms and policy guidance to determine which settings should be set on or off. Other embodiments are described and claimed.

Abstract: A system that may optionally be partitioned into multiple domains is disclosed. Each domain is capable of independently powering on, executing a firmware program, and loading an operating system, including a legacy operating system, as well as running an application program that is distinct from programs running on another domain. Interrupts, including boot interrupts, reset handlers, and inter-chassis communications are initialized differently, depending on whether the system is to be partitioned or not. The cost of redundant hardware and/or firmware is substantially avoided, yet the system fully supports multiple domains.

Abstract: A firmware-based mechanism for creating, storing and retrieving variable-length records associated with error events occurring in a computer platform. The mechanism responds to error notifications by invoking a firmware-based error-handling module. The error-handling module retrieves processor-specific error information and may also interrogate the other components of the computer platform to determine their error status. Then, according to the nature of the discovered errors, the error-handling module may assemble the retrieved error information and status information into a variable-length error record, which the error-handling module may then store in a memory. On request from a processing agent, the error-handling module may retrieve a previously-stored error record and present it to the requesting agent. Thus, the invention provides a unified and standardized approach to computer error handling at the firmware level.

Abstract: A computing device maintains coherency while supporting addition and removal of memory caching agents without rebooting the computing device.

Abstract: A method and apparatus for reading a value provided by an electronic device and using that value to derive and set a timing parameter for a bus to which the electronic device is attached.

Abstract: A method and apparatus for communicating general purpose events in-band from a downstream controller is presented.

Abstract: To prevent unauthorized access to hardware management information in an out-of-band mode, i.e., when the operating system of the hardware is not executing, a method and apparatus employ an authentication protocol. Upon receiving a request for hardware component information in a service processor that is disposed in a hardware component, which request is received as an open session request and which request passes external to an operating system controlling the hardware component, the service processor transmits a challenge string to the requesting client application. In response to a challenge response received from the requesting client application, the service processor compares the challenge response to an expected response to the challenge. The expected challenge response is calculated by the service processor. Based on the result of the comparison, the service processor transmits an authentication response to the requesting client application indicating success or failure of the authentication process.