Abstract: Aspects of the present disclosure relate to improving runtime performance of equivalence checkers by a shift left process that uses an RTL lint tool to identify RTL code that can be a source of verification complexity for the downstream equivalence checker. The RTL code is further compared to a corresponding circuit model to determine a potential gate-level location of the potentially problematic RTL code. A weight can be calculated to represent a level of verification complexity that may be generated by the particular portion of the RTL code. Further, one or more recommendations can be generated by the RTL lint tool to prevent some of the verification complexity for the downstream equivalence checker.

Abstract: A system receives a specification of a circuit design for performing simulation of the circuit design. The specification includes one or more prototyping statements. A prototyping statement is processed by simulation of the circuit design. The system generates a netlist graph based on the specification of the circuit design. The system ignores the prototyping statements while generating the netlist graph. The system modifies the netlist graph to incorporate the prototyping statements of the specification. The netlist graph is modified by adding at least a net to the netlist graph based on a prototyping statement. The system performs static analysis based on the modified netlist graph.