Patents by Inventor Mohan Paruchuri

Mohan Paruchuri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050092478
    Abstract: Further, a system is provided for dissipating heat from a semiconductor module including a semiconductor die and the unitary heat sink. The heat sink comprising a unitary body having both a porous and non-porous portion is provided. The non-porous portion is attached to the semiconductor die and configured to transfer heat to the porous portion for dissipation into the environment. In addition, a method for manufacturing the heat sink is provided.
    Type: Application
    Filed: October 30, 2003
    Publication date: May 5, 2005
    Inventors: Vivek Jairazbhoy, Mohan Paruchuri
  • Publication number: 20050083655
    Abstract: A system for dissipating heat in an electronic power module is provided. The system includes a semiconductor die, a substrate, and a heat sink in which is contained a first fluid, and a conduit through which a second fluid is permitted to flow. The substrate is attached on one surface to the die and configured to conduct heat from the die. The heat sink is attached to another surface of the substrate and transfers heat from the die to the first fluid contained therein, which evaporates due to the heat provided by the substrate. The fluid is condensed on a condensing wall cooled by the second fluid, which flows across the outer surface of the condensing wall, to transport heat away from the heat sink.
    Type: Application
    Filed: October 15, 2003
    Publication date: April 21, 2005
    Inventors: Vivek Jairazbhoy, Prathap Reddy, Mohan Paruchuri, Jay Baker
  • Patent number: 6838623
    Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: January 4, 2005
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Lawrence Kneisel, Mohan Paruchuri, Vivek Jairazboy, Vladimir Stoica
  • Patent number: 6623651
    Abstract: A method 10 for making a multi-layer electronic circuit board 98 having at least one electrically conductive protuberance 15 which forms a “via” and which traverses through the various layers of the electric circuit board 98, and further having at least one interconnection portion 102 which supports a wide variety of components and interconnection assemblies.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: September 23, 2003
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Bharat Patel, Jay D. Baker, Mohan Paruchuri
  • Patent number: 6620545
    Abstract: A device for producing an electro-motive force is disclosed. The device includes a cover for creating a liquid seal, an electrolyte contained within the cover for creating an ionic transfer path (medium), and an etched tri-metal board (substrate). The etched tri-metal board has a first conductive layer, a second conductive layer and a third conductive layer. The first, second and third conductive layers are selectively etched to form a cathode and an anode. The cover is sealed against the substrate and filled with an electrolyte to form an electrical device, such as a battery.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: September 16, 2003
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Lakhi N. Goenka, William F. Quilty, Jr., Mohan Paruchuri
  • Publication number: 20030102152
    Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.
    Type: Application
    Filed: November 20, 2002
    Publication date: June 5, 2003
    Inventors: Lawrence Leroy Kneisel, Mohan Paruchuri, Vivek Jairazbhoy, Vladimir Stoica
  • Publication number: 20020142215
    Abstract: A device for producing an electro-motive force is disclosed. The device includes a cover for creating a liquid seal, an electrolyte contained within the cover for creating an ionic transfer path (medium), and an etched tri-metal board (substrate). The etched tri-metal board has a first conductive layer, a second conductive layer and a third conductive layer. The first, second and third conductive layers are selectively etched to form a cathode and an anode. The cover is sealed against the substrate and filled with an electrolyte to form an electrical device, such as a battery.
    Type: Application
    Filed: January 5, 2001
    Publication date: October 3, 2002
    Inventors: Lakhi N. Goenka, William F. Quilty, Mohan Paruchuri
  • Publication number: 20010045407
    Abstract: A method 10 for making a multi-layer electronic circuit board 98 having at least one electrically conductive protuberance 15 which forms a “via” and which traverses through the various layers of the electric circuit board 98, and further having at least one interconnection portion 102 which supports a wide variety of components and interconnection assemblies.
    Type: Application
    Filed: March 22, 2001
    Publication date: November 29, 2001
    Inventors: Bharat Patel, Jay D. Baker, Mohan Paruchuri
  • Patent number: 6250541
    Abstract: A method which utilizes flip chip technology to provide interconnection between printed circuit boards and integrated circuits is disclosed. The method involves metallization of the bond pad and multiple, novel bump compositions and coating compositions to provide an interconnection which is reliable and which withstands differences in the coefficient of thermal expansion between the silicon device and the bump material.
    Type: Grant
    Filed: April 20, 2000
    Date of Patent: June 26, 2001
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Dongkai Shangguan, Mohan Paruchuri, Achyuta Achari
  • Patent number: 6082610
    Abstract: A method which utilizes flip chip technology to provide interconnection between printed circuit boards and integrated circuits is disclosed. The method involves metallization of the bond pad and multiple, novel bump compositions and coating compositions to provide an interconnection which is reliable and which withstands differences in the coefficient of thermal expansion between the silicon device and the bump material.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: July 4, 2000
    Assignee: Ford Motor Company
    Inventors: Dongkai Shangguan, Mohan Paruchuri, Achyuta Achari
  • Patent number: 6011313
    Abstract: A device which utilizes flip chip technology to provide interconnection between printed circuit boards and integrated circuits is disclosed. The method involves metallization of the bond pad and multiple, novel bump compositions and coating compositions to provide an interconnection which is reliable and which withstands differences in the coefficient of thermal expansion between the silicon device and the bump material.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: January 4, 2000
    Assignee: Ford Motor Company
    Inventors: Dongkai Shangguan, Mohan Paruchuri, Achyuta Achari