Abstract: A prediction model is generated for a user using data regarding how the user responded to different positionings of items of ancillary content. The prediction model is used to determine respective positionings of a plurality of items of ancillary content. The items of ancillary content are streamed to and displayed by a user device as interstitial content using the determined respective positionings. Frames of an item of primary content may be analyzed to identify appropriate interstitial insertion points and to generate labels. The labels may be utilized by a remote system to select and stream interstitial content for the insertion points. The user's location may be determined and used to determine a maximum amount of ancillary content for a corresponding time period. Different amounts of ancillary content for a given time period may be provided to different users based on a registration state.

Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

Abstract: This invention relates to a medical equipment for simultaneous diagnostic of various vital parameters of human body comprising a seating means installed with a plurality of sensors to measure various vital human body parameters, which is provided in communication with a control unit to transmit user related data to a monitoring unit. It is associated with the following advantageous features: Simultaneous diagnostic of various vital parameters of human body, hence less time consuming. Compact and therefore portable. Cost effective.

Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.

Abstract: A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.

Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.

Abstract: An information handling system (IHS), method and computer program product enables expeditious, scalable, and distributable asset location tracking in an enterprise using both passive radio frequency identification (RFID) technology and wireless communication to RFID tags. A controller of the IHS determines available source(s) of location data for a particular RFID tag from: (i) location data included in the RFID data; (ii) signal strength and direction data detected by a corresponding RFID sensor; and (iii) information indicating the zone sensed by the corresponding RFID sensor. The controller generates a standardized RFID event including a location defined in a standard spatial coordinate system in response to the one or more available sources of location data.

Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.

Abstract: In an embodiment a processing system includes a reset circuit configured to receive a reset-request signal and one or more further reset-request signals, wherein the one or more further reset-request signals are provided by a processing core, one or more further circuits and/or a terminal of the processing system and to generate a combined reset-request signal by combining the reset-request signal and the one or more further reset-request signals, and a hardware test circuit including for each of the one or more further reset-request signals, a respective first combinational circuit configured to selectively assert the respective further reset-request signal, a second combinational logic circuit configured to selectively mask the combined reset-request signal, and a control circuit configured to repeat operations during a diagnostic phase.

Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits.

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.

Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.

Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits.

Abstract: A processing system includes safety monitoring circuits configured to generate error signals by monitoring a microprocessor operations, a memory controller, and/or a resource. The system further includes fault collection sub-circuits, each including one or more error combination circuits, each including a first programmable register and being configured to receive a subset of the error signals, determine whether an error signal is asserted, and store to the first register error status data that identifies the asserted error signal. Each error combination circuit is configured to read enable data from the first register and generate a combined error signal based on the error status and enable data. The error management circuit includes a second programmable register and is configured to receive the combined error signals, read routing data from the second register, and generate for each microprocessor an error signal based on the combined error signals and routing data.

Abstract: A processing system includes a processing core including a microprocessor, a memory controller configured to read software instructions for execution by the processing core, a plurality of safety monitoring circuits configured to generate a plurality of error signals by monitoring operation of the processing core and the memory controller, a fault collection and error management circuit implemented as a hardware circuit, and a connectivity test circuit. The fault collection and error management circuit is configured to receive the plurality of error signals from the plurality of safety monitoring circuits and generate one or more reaction signals as a function of the plurality of error signals. The connectivity test circuit is configured to, during a diagnostic phase executed by the processing system after executing a reset phase and before executing a software runtime phase, test connectivity between the plurality of safety monitoring circuits and the fault collection and error management circuit.

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.

Abstract: In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first memory error packet associated with a first memory; receiving, with the first buffer, a second memory error packet associated with a second memory; transmitting a first reading request for reading the first memory error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central memory error management unit (MEMU); in response to receiving the first reading request, reading the first memory error packet from the first buffer, transmitting the first memory error packet to a controller of the central MEMU, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second memory error packet.

Abstract: A device for a system on a chip (SOC), the device includes: a comparator that includes a first input port, a second input port, and an output port. A first input signal and a second input signal are split into N bit pairs that include one bit from the first input signal and one bit from the second input signal. The comparator is configured so a mismatch between the first input signal and the second input signal causes an output signal to assume a first expected state. The device further comprises a test controller to perform a first operability test by mismatching the N bit pairs and verifying that the output signal assumes the first expected state.

Abstract: A smart guide display system identifies, for a subject object, a nearest candidate reference object in each of multiple directions (e.g., to the top, the right, the bottom, and the left of the subject object). The smart guide display system also determines the distance from the subject object to each of those nearest candidate reference objects. The smart guide display system displays equal spacing smart guides to the nearest candidate reference objects along two different axes if the distances between the subject object and those nearest reference objects are approximately equal.

Abstract: A smart guide display system generates one or more sub-objects for at least one of reference object in digital content, and each of these sub-objects is added to a set of reference objects. These sub-objects can be, for example, an edge of a reference object, a rectangle generated from a rectilinear reference object, or a freeform gradient color point included in a reference object. When a subject object is to be placed in digital content smart guides, such as equal distance guides or alignment guides, are displayed based on the objects in the set of reference objects.