Patents by Inventor Mohan V. Kalkunte

Mohan V. Kalkunte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11909670
    Abstract: The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: February 20, 2024
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Surendra Anubolu, Sachin Prabhakarrao Kadu, Laxminarasimha Rao Kesiraju, Mohan V. Kalkunte
  • Publication number: 20220321504
    Abstract: The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Inventors: Surendra ANUBOLU, Sachin Prabhakarrao KADU, Laxminarasimha Rao KESIRAJU, Mohan V. KALKUNTE
  • Patent number: 11368412
    Abstract: The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: June 21, 2022
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Surendra Anubolu, Sachin Prabhakarrao Kadu, Laxminarasimha Rao Kesiraju, Mohan V. Kalkunte
  • Publication number: 20220038394
    Abstract: The disclosed systems and methods provide methods and systems for providing power throttling adapted for high performance network switches. A method includes determining, for each of a plurality of measurement periods within a thermal average period, an energy usage estimate for a packet processing block configured to process ingress packets at a power gated clock rate. The method includes determining, for each of the plurality of measurement periods, a target clock rate for the packet processing block based on the determined energy usage estimates to meet a target energy value that is averaged for the thermal average period. The method includes adjusting, for each of the plurality of measurement periods, the power gated clock rate towards the target clock rate, wherein the adjusting causes the packet processing block to process the ingress packets at the adjusted power gated clock rate.
    Type: Application
    Filed: July 31, 2020
    Publication date: February 3, 2022
    Inventors: Surendra ANUBOLU, Sachin Prabhakarrao Kadu, Laxminarasimha Rao Kesiraju, Mohan V. Kalkunte
  • Patent number: 6977892
    Abstract: A method for preserving flow order is presented, the method comprising receiving up to a plurality of indications denoting commencement of frame transmission on a corresponding plurality of communication links, identifying that one or more of the received frames denote the start of a flow condition, and dedicating a receive buffer from a plurality of receive buffers to receive all frames associated with the identified flow condition.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: December 20, 2005
    Assignee: Nortel Networks Limited
    Inventors: Mohan V. Kalkunte, James L. Mangin, Ian Crayford
  • Patent number: 6973031
    Abstract: A method for preserving frame order across an aggregated link comprised of a plurality of virtual links each supporting a particular transmission rate is presented comprising receiving up to a plurality of indications denoting commencement of frame transmission on each of the virtual links, and assigning a plurality of pointer values to a corresponding plurality of records in a pointer value buffer associated with each of the virtual links based, at least in part, on the relative order in which data frames are transmitted on each of the virtual links.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: December 6, 2005
    Assignee: Nortel Networks Limited
    Inventors: Mohan V. Kalkunte, James L. Mangin, Ian Crayford
  • Patent number: 6970420
    Abstract: A method for preserving frame order across an aggregated link comprising receiving up to a plurality of indications denoting commencement of frame transmission on each of a plurality of virtual links each associated with a particular quality of service level comprising the aggregated link, and assigning a plurality of pointer values to a corresponding plurality of records in an appropriate ones of a plurality of pointer value buffers associated with the corresponding plurality of virtual links based, at least in part, on the relative order in which data frames are transmitted on each of the links.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: November 29, 2005
    Assignee: Nortel Networks Limited
    Inventors: Mohan V. Kalkunte, James L. Mangin, Ian Crayford
  • Patent number: 6970419
    Abstract: A method for preserving frame order of a plurality of frames transmitted over a plurality of communication links is presented. In accordance with the teachings of the present invention, the method includes receiving up to a plurality of indications denoting commencement of frame transmission on a corresponding plurality of communication links, and assigning a pointer value to a record in a buffer for each of said frames based, at least in part, on a relative order in which the indications are received.
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: November 29, 2005
    Assignee: Nortel Networks Limited
    Inventors: Mohan V. Kalkunte, James L. Mangin, Ian Crayford
  • Patent number: 6747951
    Abstract: A technique for dynamically adjusting the aging time of a shortcut virtual circuit connection (VCC) in a Multi-protocol over ATM (MPOA) client based on one or more factors. In one embodiment, a method of dynamically adjusting aging time of a shortcut VCC includes detecting a packet flow between a source and a destination, establishing a shortcut VCC between the source and destination, and adjusting an aging time of the shortcut VCC in response to the number of VCCs available by the MPOA client. In other embodiment, the aging time is dynamically adjusted based on the VCC threshold level, the protocol of the flow, and/or the application type of the flow.
    Type: Grant
    Filed: September 20, 1999
    Date of Patent: June 8, 2004
    Assignee: Nortel Networks Limited
    Inventors: Mohan V. Kalkunte, James L. Mangin, Derek H. Pitcher
  • Patent number: 6744776
    Abstract: A novel method of servicing multiple data queues having different priorities is provided in a network switch. A dequeuing logic circuit services the data queues in a round-robin fashion. Programmable number of data packets is selected from each data queue in each cycle. The dequeuing logic circuit compares the number of data packets selected from a current data queue in a current cycle with the preprogrammed number of data packets set for the current queue, and selects a data packet from the current data queue only if the number of packets selected from the current data queue in the current cycle is less than the preprogrammed number. Selection of a data packet from the current data queue is bypassed, processing a next data queue, if the number of packets selected from the current data queue in the current cycle is not less than the preprogrammed number.
    Type: Grant
    Filed: October 18, 2000
    Date of Patent: June 1, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohan V. Kalkunte, Shashank Merchant, Phil Simons
  • Patent number: 6704280
    Abstract: A flow of information over a network is controlled by a policing function placed at a data link layer of the network. For a full-duplex architecture, an accumulated count value for each packet of information received as input by a switching device is ascertained during a predetermined interval. The policing function at a data link layer determines if the accumulated count value has exceeded an interval bit rate based on a transmission rate set by a traffic contract at a networking layer higher than the data link layer. In response to the accumulated count value exceeding the interval bit rate, the switching device sends a PAUSE frame to halt transmission of the information. The half-duplex architecture, collision based backpressure and carrier-sense backpressure techniques are used by the policing function for enforcement of the traffic contracts.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: March 9, 2004
    Assignee: Nortel Networks Limited
    Inventors: James L. Mangin, Mohan V. Kalkunte, Sanjay Munshi
  • Publication number: 20030202472
    Abstract: A method for preserving flow order is presented, the method comprising receiving up to a plurality of indications denoting commencement of frame transmission on a corresponding plurality of communication links, identifying that one or more of the received frames denote the start of a flow condition, and dedicating a receive buffer from a plurality of receive buffers to receive all frames associated with the identified flow condition.
    Type: Application
    Filed: December 17, 1998
    Publication date: October 30, 2003
    Inventors: MOHAN V. KALKUNTE, JAMES L. MANGIN, IAN CRAYFORD
  • Patent number: 6335939
    Abstract: A repeater provides an efficient interconnection of an IEEE 802.3 10 Mb/s network with an IEEE 802.3 100 Mb/s network using minimal buffering. The repeater includes a filter that selectively outputs a data packet, received from the 100 Mb/s network, to the 10 Mb/s network based on the destination address in the received data packet. Specifically, the filter passes all data packets in the 10 Mb/s domain to the 100 Mb/s domain. The filter selectively passes the data packet from the 100 Mb/s domain to the 10 Mb/s domain by determining if the received data packet includes a destination address value that specifies transmission of the data packet to the 10 Mb/s network. If the destination address value does not specify a multicast value or an address of a network node in the 10 Mb/s network, the filter discards the data packet.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: January 1, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganatios Y. Hanna, Mohan V. Kalkunte, Rudolph J. Sterner
  • Patent number: 6330248
    Abstract: A gigabit network node having a media access controller outputting data frames at gigabit rates uses multiple 100 MB/s media interface links coupled to a physical interface to enable implementation of a gigabit network using low cost data links. A modified reconciliation layer, also referred to as a media interface, receives a data frame from a gigabit MAC and selectively stores the received packet data into one of a plurality of transmit buffers associated with the respective 100 MB/s media interface links, according to a path selection arbitration logic in the media interface. The path selection arbitration logic may operate according to an equal priority scheme, where each received data frame is routed according to a round-robin scheme.
    Type: Grant
    Filed: December 5, 1997
    Date of Patent: December 11, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gopal S. Krishna, Mohan V. Kalkunte, Shashank C. Merchant
  • Patent number: 6252880
    Abstract: A buffered distributor having a plurality of network ports serving respective network nodes includes a distribution core having a filter for selectively supplying a data packet to a selected network port based on the destination address of the received data packet relative to the network address of the network node corresponding to the selected network port. The buffered distributor distributes the received data packet to all network ports. Each network port includes a transmit buffer that loads the distributed data packet in response to an enable signal from the distribution core. The filter logic outputs a filter signal that prevents generation of the enable signal for a selected transmit buffer if a review of the destination address indicates the distributed data packet is not relevant to the corresponding network port.
    Type: Grant
    Filed: November 10, 1997
    Date of Patent: June 26, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ganatios Y. Hanna, Mohan V. Kalkunte
  • Patent number: 6195334
    Abstract: A network switch in a packet switched network has multiple network ports, each having a physical layer transceiver, a media access controller, transmit and receive buffers, and a bus interface for transferring data using a host processor. The network switch includes a low-latency mode, where a transfer request is initiated by a network switch port when the receive buffer includes 16 bytes of packet data. If during transfer the MAC detects a collision on the shared network medium, the network port generates a HALT signal in response to detecting a collision, enabling the host controller transferring data from the network port to abort the transfer, and begin transfer on another port. Status information also is stored in the receive buffer in response to the detected collision. Generation of the HALT signal enables the network switch to operate in low-latency mode without requiring substantial resources by the host processor to filter collision fragments or runt packets.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: February 27, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jayant Kadambi, Mohan V. Kalkunte
  • Patent number: 6141327
    Abstract: A network station transmitting on a half-duplex Ethernet (802.3) half-duplex media includes a delay credit counter that tracks a delay interval after transmission of a data packet to ensure the network station operates according to an assigned transmission rate. The delay credit counter is decremented by a delay count calculated based on the number of transmitted data bytes and the assigned rate of the network station, and incremented during non-transmitting (i.e., idle) intervals by the network station. The network station defers from transmitting on the half-duplex network media until the delay credit counter has a counter value greater than or equal to zero, resulting in a reduced number of collisions between network stations.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: October 31, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohan V. Kalkunte, Ganatios Y. Hanna
  • Patent number: 6118787
    Abstract: A network interface for a shared gigabit Ethernet network selectively modulates an interpacket gap interval following a burst transmission in order to establish a rotating priority arrangement with network stations on the gigabit network. A network station includes a programmable burst timer that counts a burst interval corresponding to a negotiated bandwidth. The network station having accessed the media continues to transmit data packets so long as data is available in a transmit buffer, and the burst timer has not expired. Each data packet within the burst is transmitted after waiting a minimum interpacket gap interval of 96 bit times. Following the burst transmission, the network interface waits a modified delay interval equal to the minimum interpacket gap plus a multiple number of slot times related to the number of stations on the network. The modified delay interval is decremented by a slot time each time the network station detects a burst transmission by another network station.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: September 12, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohan V. Kalkunte, Jayant Kadambi
  • Patent number: 6118761
    Abstract: A network switch in a full-duplex IEEE 802.3 network includes a data monitor module that monitors data utilization between ports. Upon detection of a congestion condition in an output buffer, the data monitor module determines for each of the remaining network switch ports a traffic contribution relative to the total network traffic received by the one congested network switch port. The network switch includes a rate controller that generates rate control frames for the remaining network switch ports, where each rate control frame specifies a transmission rate for the transmitting network node based on the corresponding traffic contribution by the network node. The outputting of a rate control frame to a network node based on the corresponding traffic contribution optimizes elimination of the congestion condition by prioritizing the generation of rate control frames for the network node most responsible for creating the congestion condition.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: September 12, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohan V. Kalkunte, Jayant Kadambi
  • Patent number: 6115356
    Abstract: A network switch in a full-duplex IEEE 802.3 network includes a data monitor module that monitors data utilization between ports. Upon detection of a congestion condition in an output buffer, the data monitor module determines for each of the remaining network switch ports a traffic contribution relative to the total network traffic received by the one congested network switch port. The network switch includes a pause controller that generates pause control frames for the remaining network switch ports, where each pause control frame specifies a corresponding interval having a duration based on the traffic contribution by the corresponding network node. The outputting of a pause control frame to a network node based on the corresponding traffic contribution optimizes elimination of the congestion condition by prioritizing the generation of pause frames for the network node most responsible for creating the congestion condition.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: September 5, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohan V. Kalkunte, Jayant Kadambi