Patents by Inventor Mohan Vamsi Dunga

Mohan Vamsi Dunga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250006244
    Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes. The control means is configured to apply a plurality of pulses of a program voltage increasing in magnitude by a program step amount to selected ones of the plurality of word lines while applying at least one pass voltage to unselected ones of the plurality of word lines during a plurality of programming loops of a programming operation. The control means is also configured to adjust the at least one pass voltage based on the program voltage.
    Type: Application
    Filed: August 14, 2023
    Publication date: January 2, 2025
    Applicant: Western Digital Technologies, Inc.
    Inventors: Mohan Vamsi Dunga, Xiang Yang
  • Publication number: 20240386930
    Abstract: A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines. Some of the word line switch transistors have a first width and some of the word line switch transistors have a second width that is different than the first width. By providing the word line switch transistors with different widths, the size of a word line switch area in the memory device can be optimized.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 21, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Mohan Vamsi Dunga, Xiang Yang, Keyur Payak
  • Patent number: 10818366
    Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: October 27, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohan Vamsi Dunga, Changyuan Chen, Biswajit Ray
  • Publication number: 20200152281
    Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.
    Type: Application
    Filed: January 15, 2020
    Publication date: May 14, 2020
    Inventors: Mohan Vamsi DUNGA, Changyuan CHEN, Biswajit RAY
  • Patent number: 10553294
    Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohan Vamsi Dunga, Changyuan Chen, Biswajit Ray
  • Patent number: 10541031
    Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: January 21, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mohan Vamsi Dunga, Piyush Dak, Pitamber Shukla
  • Publication number: 20190385680
    Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Applicant: SanDisk Technologies LLC
    Inventors: Mohan Vamsi Dunga, Piyush Dak, Pitamber Shukla
  • Patent number: 10460814
    Abstract: Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 29, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Piyush Dak, Mohan Vamsi Dunga, Pitamber Shukla
  • Publication number: 20190180823
    Abstract: Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Inventors: Piyush DAK, Mohan Vamsi DUNGA, Pitamber SHUKLA
  • Patent number: 10304559
    Abstract: A device is disclosed that includes a data write engine configured to store data into a block of a memory. The device also includes a post-write read engine configured to adjust a read voltage responsive to an output of the temperature sensor and to read stored data from the block based on the adjusted read voltage to verify integrity of the data. The device also includes a block manager configured to initiate a corrective operation responsive to an error characteristic of the data read from the block.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 28, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Himanshu Hemant Naik, Biswajit Ray, Mohan Vamsi Dunga, Changyuan Chen
  • Publication number: 20190156902
    Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Inventors: Mohan Vamsi DUNGA, Changyuan CHEN, Biswajit RAY
  • Patent number: 10269439
    Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: April 23, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohan Vamsi Dunga, Changyuan Chen, Biswajit Ray
  • Publication number: 20180286487
    Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.
    Type: Application
    Filed: March 28, 2017
    Publication date: October 4, 2018
    Applicant: Western Digital Technologies, Inc.
    Inventors: Mohan Vamsi Dunga, Changyuan Chen, Biswajit Ray
  • Publication number: 20180189135
    Abstract: A device is disclosed that includes a data write engine configured to store data into a block of a memory. The device also includes a post-write read engine configured to adjust a read voltage responsive to an output of the temperature sensor and to read stored data from the block based on the adjusted read voltage to verify integrity of the data. The device also includes a block manager configured to initiate a corrective operation responsive to an error characteristic of the data read from the block.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: HIMANSHU HEMANT NAIK, BISWAJIT RAY, MOHAN VAMSI DUNGA, CHANGYUAN CHEN
  • Patent number: 9368222
    Abstract: Disclosed herein are techniques for pre-charging channels when programming memory cells. A pre-charge voltage is applied to both selected bit lines and inhibited bit lines during a channel pre-charge phase. The pre-charge voltage is passed to the channels of NAND strings. The voltage on the inhibited bit lines is then reduced to a program inhibit voltage. Also, the voltage on the selected bit lines is reduced to a program enable voltage. Further, the pre-charge voltage from the channels of the selected NAND strings is discharged while maintaining the pre-charge voltage in the channels of the inhibited NAND strings. The potential in the channels of the inhibited NAND strings may then be boosted and a programming voltage may be applied to a selected word line.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: June 14, 2016
    Assignee: SanDisk Technologies Inc.
    Inventors: Mohan Vamsi Dunga, Masaaki Higashitani
  • Publication number: 20160099066
    Abstract: Disclosed herein are techniques for pre-charging channels when programming memory cells. A pre-charge voltage is applied to both selected bit lines and inhibited bit lines during a channel pre-charge phase. The pre-charge voltage is passed to the channels of NAND strings. The voltage on the inhibited bit lines is then reduced to a program inhibit voltage. Also, the voltage on the selected bit lines is reduced to a program enable voltage. Further, the pre-charge voltage from the channels of the selected NAND strings is discharged while maintaining the pre-charge voltage in the channels of the inhibited NAND strings. The potential in the channels of the inhibited NAND strings may then be boosted and a programming voltage may be applied to a selected word line.
    Type: Application
    Filed: October 1, 2014
    Publication date: April 7, 2016
    Inventors: Mohan Vamsi Dunga, Masaaki Higashitani
  • Patent number: 9142305
    Abstract: A system for erasing a non-volatile storage system that reduces the voltage across the word line select transistors which interface between the word lines and global control lines. The use of the lower voltage across the word line select transistors allows for the word line select transistors to be made smaller. The use of smaller components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: September 22, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Mohan Vamsi Dunga, Man Mui, Masaaki Higashitani, Fumiaki Toyama
  • Patent number: 8937837
    Abstract: A system for erasing non-volatile storage system that reduces the voltage across the transistor that interfaces between the sense amplifier and the bit line so that the transistor can be made smaller. Additionally, the use of the lower voltage allows for various components to be positioned closer to each other. The use of smaller components and smaller spaces between components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: January 20, 2015
    Assignee: Sandisk Technologies Inc.
    Inventors: Mohan Vamsi Dunga, Kwang-Ho Kim, Masaaki Higashitani
  • Publication number: 20140003150
    Abstract: A system for erasing a non-volatile storage system that reduces the voltage across the word line select transistors which interface between the word lines and global control lines. The use of the lower voltage across the word line select transistors allows for the word line select transistors to be made smaller. The use of smaller components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.
    Type: Application
    Filed: June 11, 2013
    Publication date: January 2, 2014
    Inventors: Mohan Vamsi Dunga, Man Mui, Masaaki Higashitani, Fumiaki Toyama
  • Publication number: 20130301358
    Abstract: A system for erasing non-volatile storage system that reduces the voltage across the transistor that interfaces between the sense amplifier and the bit line so that the transistor can be made smaller. Additionally, the use of the lower voltage allows for various components to be positioned closer to each other. The use of smaller components and smaller spaces between components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.
    Type: Application
    Filed: May 3, 2013
    Publication date: November 14, 2013
    Applicant: SANDISK TECHNOLOGIES, INC.
    Inventors: Mohan Vamsi Dunga, Kwang-Ho Kim, Masaaki Higashitani