Patents by Inventor Mohan Vamsi Dunga
Mohan Vamsi Dunga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250006244Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes. The control means is configured to apply a plurality of pulses of a program voltage increasing in magnitude by a program step amount to selected ones of the plurality of word lines while applying at least one pass voltage to unselected ones of the plurality of word lines during a plurality of programming loops of a programming operation. The control means is also configured to adjust the at least one pass voltage based on the program voltage.Type: ApplicationFiled: August 14, 2023Publication date: January 2, 2025Applicant: Western Digital Technologies, Inc.Inventors: Mohan Vamsi Dunga, Xiang Yang
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Publication number: 20240386930Abstract: A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines. Some of the word line switch transistors have a first width and some of the word line switch transistors have a second width that is different than the first width. By providing the word line switch transistors with different widths, the size of a word line switch area in the memory device can be optimized.Type: ApplicationFiled: August 1, 2023Publication date: November 21, 2024Applicant: Western Digital Technologies, Inc.Inventors: Mohan Vamsi Dunga, Xiang Yang, Keyur Payak
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Patent number: 10818366Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.Type: GrantFiled: January 15, 2020Date of Patent: October 27, 2020Assignee: Western Digital Technologies, Inc.Inventors: Mohan Vamsi Dunga, Changyuan Chen, Biswajit Ray
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Publication number: 20200152281Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Mohan Vamsi DUNGA, Changyuan CHEN, Biswajit RAY
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Patent number: 10553294Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.Type: GrantFiled: January 25, 2019Date of Patent: February 4, 2020Assignee: Western Digital Technologies, Inc.Inventors: Mohan Vamsi Dunga, Changyuan Chen, Biswajit Ray
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Patent number: 10541031Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.Type: GrantFiled: June 15, 2018Date of Patent: January 21, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Mohan Vamsi Dunga, Piyush Dak, Pitamber Shukla
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Publication number: 20190385680Abstract: A program circuit may two-dimensionally program data into cells by applying different selected bit line or channel voltages to different bit lines or channels located in different bit line zones of a block during a program operation. The block may be further separated or divided into word line zones. The program circuit may adjust the different bit line or channel voltages as it programs in different word line zones of the block. In accordance with the two-dimensional programming, the program circuit may perform single-pulse program-only SLC program operations.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Applicant: SanDisk Technologies LLCInventors: Mohan Vamsi Dunga, Piyush Dak, Pitamber Shukla
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Patent number: 10460814Abstract: Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.Type: GrantFiled: December 12, 2017Date of Patent: October 29, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Piyush Dak, Mohan Vamsi Dunga, Pitamber Shukla
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Publication number: 20190180823Abstract: Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.Type: ApplicationFiled: December 12, 2017Publication date: June 13, 2019Inventors: Piyush DAK, Mohan Vamsi DUNGA, Pitamber SHUKLA
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Patent number: 10304559Abstract: A device is disclosed that includes a data write engine configured to store data into a block of a memory. The device also includes a post-write read engine configured to adjust a read voltage responsive to an output of the temperature sensor and to read stored data from the block based on the adjusted read voltage to verify integrity of the data. The device also includes a block manager configured to initiate a corrective operation responsive to an error characteristic of the data read from the block.Type: GrantFiled: December 30, 2016Date of Patent: May 28, 2019Assignee: Western Digital Technologies, Inc.Inventors: Himanshu Hemant Naik, Biswajit Ray, Mohan Vamsi Dunga, Changyuan Chen
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Publication number: 20190156902Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.Type: ApplicationFiled: January 25, 2019Publication date: May 23, 2019Inventors: Mohan Vamsi DUNGA, Changyuan CHEN, Biswajit RAY
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Patent number: 10269439Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.Type: GrantFiled: March 28, 2017Date of Patent: April 23, 2019Assignee: Western Digital Technologies, Inc.Inventors: Mohan Vamsi Dunga, Changyuan Chen, Biswajit Ray
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Publication number: 20180286487Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.Type: ApplicationFiled: March 28, 2017Publication date: October 4, 2018Applicant: Western Digital Technologies, Inc.Inventors: Mohan Vamsi Dunga, Changyuan Chen, Biswajit Ray
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Publication number: 20180189135Abstract: A device is disclosed that includes a data write engine configured to store data into a block of a memory. The device also includes a post-write read engine configured to adjust a read voltage responsive to an output of the temperature sensor and to read stored data from the block based on the adjusted read voltage to verify integrity of the data. The device also includes a block manager configured to initiate a corrective operation responsive to an error characteristic of the data read from the block.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Inventors: HIMANSHU HEMANT NAIK, BISWAJIT RAY, MOHAN VAMSI DUNGA, CHANGYUAN CHEN
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Patent number: 9368222Abstract: Disclosed herein are techniques for pre-charging channels when programming memory cells. A pre-charge voltage is applied to both selected bit lines and inhibited bit lines during a channel pre-charge phase. The pre-charge voltage is passed to the channels of NAND strings. The voltage on the inhibited bit lines is then reduced to a program inhibit voltage. Also, the voltage on the selected bit lines is reduced to a program enable voltage. Further, the pre-charge voltage from the channels of the selected NAND strings is discharged while maintaining the pre-charge voltage in the channels of the inhibited NAND strings. The potential in the channels of the inhibited NAND strings may then be boosted and a programming voltage may be applied to a selected word line.Type: GrantFiled: October 1, 2014Date of Patent: June 14, 2016Assignee: SanDisk Technologies Inc.Inventors: Mohan Vamsi Dunga, Masaaki Higashitani
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Publication number: 20160099066Abstract: Disclosed herein are techniques for pre-charging channels when programming memory cells. A pre-charge voltage is applied to both selected bit lines and inhibited bit lines during a channel pre-charge phase. The pre-charge voltage is passed to the channels of NAND strings. The voltage on the inhibited bit lines is then reduced to a program inhibit voltage. Also, the voltage on the selected bit lines is reduced to a program enable voltage. Further, the pre-charge voltage from the channels of the selected NAND strings is discharged while maintaining the pre-charge voltage in the channels of the inhibited NAND strings. The potential in the channels of the inhibited NAND strings may then be boosted and a programming voltage may be applied to a selected word line.Type: ApplicationFiled: October 1, 2014Publication date: April 7, 2016Inventors: Mohan Vamsi Dunga, Masaaki Higashitani
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Patent number: 9142305Abstract: A system for erasing a non-volatile storage system that reduces the voltage across the word line select transistors which interface between the word lines and global control lines. The use of the lower voltage across the word line select transistors allows for the word line select transistors to be made smaller. The use of smaller components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.Type: GrantFiled: June 11, 2013Date of Patent: September 22, 2015Assignee: SanDisk Technologies Inc.Inventors: Mohan Vamsi Dunga, Man Mui, Masaaki Higashitani, Fumiaki Toyama
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Patent number: 8937837Abstract: A system for erasing non-volatile storage system that reduces the voltage across the transistor that interfaces between the sense amplifier and the bit line so that the transistor can be made smaller. Additionally, the use of the lower voltage allows for various components to be positioned closer to each other. The use of smaller components and smaller spaces between components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.Type: GrantFiled: May 3, 2013Date of Patent: January 20, 2015Assignee: Sandisk Technologies Inc.Inventors: Mohan Vamsi Dunga, Kwang-Ho Kim, Masaaki Higashitani
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Publication number: 20140003150Abstract: A system for erasing a non-volatile storage system that reduces the voltage across the word line select transistors which interface between the word lines and global control lines. The use of the lower voltage across the word line select transistors allows for the word line select transistors to be made smaller. The use of smaller components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.Type: ApplicationFiled: June 11, 2013Publication date: January 2, 2014Inventors: Mohan Vamsi Dunga, Man Mui, Masaaki Higashitani, Fumiaki Toyama
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Publication number: 20130301358Abstract: A system for erasing non-volatile storage system that reduces the voltage across the transistor that interfaces between the sense amplifier and the bit line so that the transistor can be made smaller. Additionally, the use of the lower voltage allows for various components to be positioned closer to each other. The use of smaller components and smaller spaces between components allows the non-volatile storage system to include more memory cells, thereby providing the ability to store more data.Type: ApplicationFiled: May 3, 2013Publication date: November 14, 2013Applicant: SANDISK TECHNOLOGIES, INC.Inventors: Mohan Vamsi Dunga, Kwang-Ho Kim, Masaaki Higashitani