Patents by Inventor Mohd Salimin Sahludin

Mohd Salimin Sahludin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wedge bond foot jumper connections
    Patent number: 9236363
    Abstract: A semiconductor device includes a substrate, first and second bond pad structures supported by the substrate and spaced from one another by a gap, and a wire bond foot jumper extending across the gap and bonded to the first and second bond pad structures.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: January 12, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jeffrey K. Jones, Basim H. Noori, Mohd Salimin Sahludin, Fernando A. Santos
  • Wedge Bond Foot Jumper Connections
    Publication number: 20150262961
    Abstract: A semiconductor device includes a substrate, first and second bond pad structures supported by the substrate and spaced from one another by a gap, and a wire bond foot jumper extending across the gap and bonded to the first and second bond pad structures.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 17, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jeffrey K. Jones, Basim H. Noori, Mohd Salimin Sahludin, Fernando A. Santos
  • Self-defining, low capacitance wire bond pad
    Patent number: 8890339
    Abstract: A bond pad region is provided that reduces parasitic capacitance generated between bond pad metallization and underlying silicon by reducing the effective area of the bond pad, while maintaining flexibility of wire bond sites and ensuring mechanical integrity of the wire bonds. Embodiments provide, in a region that would be populated by a traditional bus bar bond pad, a small bus bar bond pad that is less than half the area of the region and populating at least a portion of the remaining area with metal tiles that are not electrically connected to the small bus bar bond pad or to each other. The metal tiles provide an attachment area for at least a portion of one or more wire bonds. Only those tiles involved in connection to a wire bond contribute to parasitic capacitance, along with the small bus bar pad.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: November 18, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Fernando A. Santos, Margaret A. Szymanowski, Mohd Salimin Sahludin
  • SELF-DEFINING, LOW CAPACITANCE WIRE BOND PAD
    Publication number: 20140319703
    Abstract: A bond pad region is provided that reduces parasitic capacitance generated between bond pad metallization and underlying silicon by reducing the effective area of the bond pad, while maintaining flexibility of wire bond sites and ensuring mechanical integrity of the wire bonds. Embodiments provide, in a region that would be populated by a traditional bus bar bond pad, a small bus bar bond pad that is less than half the area of the region and populating at least a portion of the remaining area with metal tiles that are not electrically connected to the small bus bar bond pad or to each other. The metal tiles provide an attachment area for at least a portion of one or more wire bonds. Only those tiles involved in connection to a wire bond contribute to parasitic capacitance, along with the small bus bar pad.
    Type: Application
    Filed: April 30, 2013
    Publication date: October 30, 2014
    Inventors: Fernando A. Santos, Margaret A. Szymanowski, Mohd Salimin Sahludin