Patents by Inventor Mohd Yusuf Tura Ali

Mohd Yusuf Tura Ali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220408565
    Abstract: An electronic circuit, comprising: an integrated substrate structure comprising one or more electrically conductive traces comprising plating on a laser-etched, non-conductive isolated portion of the integrated substrate structure defining each electrically conductive trace; one or more electrically conductive pads at one or more predetermined positions along the one or more electrically conductive traces; and an electrical component surface mounted to the at least one electrically conductive pad with interconnect and bonding material.
    Type: Application
    Filed: July 5, 2022
    Publication date: December 22, 2022
    Applicant: Jabil Inc.
    Inventors: Weiping (aka Jonathan) Wu, Mohd Yusuf Tura Ali, Zambri Samsudin
  • Publication number: 20210360781
    Abstract: A system and method for forming a stretchable conductive circuit package that utilizes an addition and condensation mechanism incorporated into one system. When the stretchable conductive ink is used in a circuit package, the circuit package has high reliability and durability.
    Type: Application
    Filed: May 8, 2018
    Publication date: November 18, 2021
    Applicant: Jabil Inc.
    Inventors: Fakhrozi Che Ani, Zambri Bin Samsudin, Mohd Yusuf Tura Ali, Zulkifli Ahmad
  • Publication number: 20200205295
    Abstract: A method for forming a circuit pattern on an integrated substrate structure includes providing an insulating surface which includes a pattern forming portion. An activation ink is deposited only on the pattern forming portion to form a non-conductive isolation layer. A first metal layer is formed on the non-conductive isolation layer by electroless plating. A patterned portion of the first metal layer is isolated from a remaining portion of the first metal layer to form the circuit pattern. A non-conductive masking layer is applied on the first metal layer. A second metal layer is formed on the non-conductive masking layer. A surface mount land pattern and pad configuration is determined. A solder mask layer is applied to the patterned portion. A protective layer is applied to protect pad areas not covered by the solder mask layer. An electrical component may then be mounted to the pad(s).
    Type: Application
    Filed: June 15, 2017
    Publication date: June 25, 2020
    Applicant: Jabil Inc.
    Inventors: Weiping (aka Jonathan) Wu, Mohd Yusuf Tura Ali, Zambri Samsudin