Patents by Inventor Mohit Arora
Mohit Arora has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250132270Abstract: A chip package includes a package substrate and an integrated circuit (IC) die disposed on the package substrate. The IC dies includes a security asset. The chip package also includes a glass based shield selectively disposed on the IC die and above the security asset. The glass based shield is configured to block access to the security asset. In some embodiments, the chip package includes an oxide layer disposed between the glass based shield and the IC die. In some embodiments, the chip package includes a detection module and a wire connecting the detection module to the glass based shield. The detection module is configured to generate and send a serial bit stream to the glass based shield. The detection module is also configured to monitor for changes in the serial bit stream returning from the glass based shield. Changes detected in the serial bit stream indicates the glass based shield has been tampered.Type: ApplicationFiled: October 23, 2023Publication date: April 24, 2025Inventors: Mohit ARORA, Deepak Vasant KULKARNI, Richard E. GEORGE, Terry Eugene RICHARDSON
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Patent number: 12143265Abstract: Methods and systems for managing entitlements for data processing systems are disclosed. A management controller for the data processing system may utilize an out of band communication channel to obtain a list of the entitlements for the data processing system from a management server. The management controller may compare the features included in the list of the entitlements to features included in a list of existing enabled features for the data processing system to obtain a difference. The management controller may modify operation of hardware components of the data processing system to resolve the difference. By doing so, the management controller may monitor entitlements for the data processing system, the entitlements being based on user subscriptions for features of the data processing system.Type: GrantFiled: October 31, 2023Date of Patent: November 12, 2024Assignee: Dell Products L.P.Inventors: Bassem El-Azzami, Richard M. Tonry, Abeye Teshome, Mohit Arora, Vinodkumar Vasudev Ottar, Adolfo Sandor Montero, Luis Antonio Valencia Reyes, Rajaravi Chandra Kollarapu
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Patent number: 12135805Abstract: An information handling system may include at least one processor and a non-transitory, computer-reading medium having instructions thereon that are executable by the at least one processor for: providing access to one or more objects via a plurality of application programming interface (API) endpoints; receiving a call to a particular API endpoint from an app; and determining, based on a security identifier (SID) of the app, whether the call should be allowed; wherein the SID of the app is based on one or more custom capabilities defined in a manifest of the app.Type: GrantFiled: July 23, 2021Date of Patent: November 5, 2024Assignee: Dell Products L.P.Inventors: Mohit Arora, Danilo O. Tan, Zheng Yuan
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Patent number: 12126595Abstract: In an embodiment, a System-on-Chip (SoC) may include: a plurality of core domains, and a memory coupled to the plurality of core domains through a hardware firewall, wherein the hardware firewall is configured to enforce an adaptive Deny-By-Default (DBD) access policy in response to an event. In another embodiment, a circuit, may include: an access control policy generator configured to produce an adaptive DBD policy, and a hardware firewall coupled to the access control policy generator, the hardware firewall configured to enforce the adaptive DBD policy. In yet another embodiment, a method may include: storing an indication of a first DBD configuration state, the first DBD configuration state usable to enforce a first DBD access control policy, and changing the stored indication to a second DBD configuration state, the second DBD configuration state usable to enforce a second DBD access control policy.Type: GrantFiled: November 30, 2021Date of Patent: October 22, 2024Assignee: NXP USA, Inc.Inventors: Mohit Arora, Lawrence Loren Case, Joseph Charles Circello, Michael Charles Elsasser
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Patent number: 12099434Abstract: A method for managing user stories in software development via artificial intelligence is disclosed. The method includes aggregating, via an application programming interface, raw data from a software development framework according to a predetermined schedule, the raw data corresponding to user stories from a plurality of users in a natural language format; ingesting the aggregated raw data to generate structured data sets; generating a language model by using a neural network and the structured data sets, the neural network including a transformer component; training, by using the structured data sets, the language model based on predetermined criterions; tuning the trained language model for tasks by adjusting parameters; and exposing, via a communication interface, the tuned language model.Type: GrantFiled: January 3, 2023Date of Patent: September 24, 2024Assignee: JPMORGAN CHASE BANK, N.A.Inventors: Mohit Arora, Santosh Chikoti, Murali Yaddanapudi, Sai Gumma
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Patent number: 12061459Abstract: A method for automatically scaling a number of robots leveraging interactive sessions to be used within a system infrastructure, dynamically based on workload, is provided. The method includes: receiving a request for a number of robots to be provisioned within the system infrastructure; validating an availability of the requested number of robots; monitoring a CPU utilization and a memory utilization within the system infrastructure; adjusting the requested number of robots based on the CPU utilization and/or the memory utilization; and releasing the adjusted number of robots for facilitating use thereof to perform corresponding tasks within the system infrastructure.Type: GrantFiled: March 24, 2021Date of Patent: August 13, 2024Assignee: JPMORGAN CHASE BANK, N.A.Inventors: Mohit Arora, Rajeev Salaria, Sanjay Venkittan, Ravi Kappagantu
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Publication number: 20240168862Abstract: A method for managing user stories in software development via artificial intelligence is disclosed. The method includes aggregating, via an application programming interface, raw data from a software development framework according to a predetermined schedule, the raw data corresponding to user stories from a plurality of users in a natural language format; ingesting the aggregated raw data to generate structured data sets; generating a language model by using a neural network and the structured data sets, the neural network including a transformer component; training, by using the structured data sets, the language model based on predetermined criterions; tuning the trained language model for tasks by adjusting parameters; and exposing, via a communication interface, the tuned language model.Type: ApplicationFiled: January 3, 2023Publication date: May 23, 2024Applicant: JPMorgan Chase Bank, N.A.Inventors: Mohit ARORA, Santosh CHIKOTI, Murali YADDANAPUDI, Sai GUMMA
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Publication number: 20240037244Abstract: A disclosed method for managing enterprise security posture includes maintaining a security system repository (SSR) including information mapping one or more software libraries to vulnerability information indicative of one or more identified vulnerabilities, providing one or more library scanning tools configured to scan the one or more software libraries and provide notifications indicative of one or more new vulnerabilities, generating an SSR catalog indicative of vulnerability information pertaining to the one or more software libraries, and an enhanced plugin module (EPM) is provided wherein the EPM is configured to consume installed application metadata enabling to produce an inventory indicative of updates to deploy.Type: ApplicationFiled: July 29, 2022Publication date: February 1, 2024Applicant: Dell Products L.P.Inventors: Prasanth Raghavendra K S, Mohit ARORA, Ratan Kumar NAIK
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Publication number: 20230171229Abstract: In an embodiment, a System-on-Chip (SoC) may include: a plurality of core domains, and a memory coupled to the plurality of core domains through a hardware firewall, wherein the hardware firewall is configured to enforce an adaptive Deny-By-Default (DBD) access policy in response to an event. In another embodiment, a circuit, may include: an access control policy generator configured to produce an adaptive DBD policy, and a hardware firewall coupled to the access control policy generator, the hardware firewall configured to enforce the adaptive DBD policy. In yet another embodiment, a method may include: storing an indication of a first DBD configuration state, the first DBD configuration state usable to enforce a first DBD access control policy, and changing the stored indication to a second DBD configuration state, the second DBD configuration state usable to enforce a second DBD access control policy.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Applicant: NXP USA, Inc.Inventors: Mohit Arora, Lawrence Loren Case, Joseph Charles Circello, Michael Charles Elsasser
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Patent number: 11630899Abstract: An information handling system may include a processor to execute code of a threat level detection module to receive and store in memory labeled data descriptive of operating environment variables related to the information handling system including operating environment variables selected from a basic input/output system (BIOS) setting, an information handling system hardware setting, and at least one of an operating system (OS) environment setting, a developer tool access setting, or a network setting; the processor to determine, via execution of a machine learning process of the threat level detection module, a threat level value; and a security module associated with a first application executed on the information handling system to: map the threat level value with the first application; and adjust the security level associated with the first application based on the provided threat level value to modify security checks operating with the first application.Type: GrantFiled: August 1, 2019Date of Patent: April 18, 2023Assignee: Dell Products, LPInventors: Nikhil M. Vichare, Mohit Arora, Danilo O. Tan
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Patent number: 11611426Abstract: A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.Type: GrantFiled: September 9, 2021Date of Patent: March 21, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nageswara Rao Kunchapu, Tamal Das, Akshay Karkal Kamath, Mohit Arora
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Patent number: 11586476Abstract: An integrated circuit includes a primary initiator domain (ID) circuit including having a processor core, a responder domain (RD) control circuit, and a reset controller. Secondary ID circuits, each include a processor core and a reset controller. RD circuitry is coupled to communicate with the primary ID circuit and the secondary ID circuits and includes RD resource circuits. The RD control circuit is configured to allocate each of the RD resource circuits to a first initiator domain consisting of the primary ID circuit or one of the secondary ID circuits, and when one of the secondary ID circuits enters a reset mode of operation, the RD resource circuit allocated to the one of the secondary ID circuits enters a reset while the remaining RD resource circuits are not affected by the reset.Type: GrantFiled: May 24, 2021Date of Patent: February 21, 2023Assignee: NXP USA, Inc.Inventors: Mohit Arora, Milton Hissasi Kataoka, Marcos da Costa Barros, Tuongvu Van Nguyen, Rob Cosaro
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Patent number: 11582238Abstract: An information handling system may identify a process identifier of a client application that has requested a connection with the information handling system. The information handling system may obtain an access control list of a process associated with the process identifier. The information handling system may determine whether to establish a connection between the client application and the information handling system based, at least in part, on analysis of the access control list.Type: GrantFiled: August 13, 2019Date of Patent: February 14, 2023Assignee: Dell Products L.P.Inventors: Abu Shaher Sanaullah, Mohit Arora
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Publication number: 20230026040Abstract: An information handling system may include at least one processor and a non-transitory, computer-reading medium having instructions thereon that are executable by the at least one processor for: providing access to one or more objects via a plurality of application programming interface (API) endpoints; receiving a call to a particular API endpoint from an app; and determining, based on a security identifier (SID) of the app, whether the call should be allowed; wherein the SID of the app is based on one or more custom capabilities defined in a manifest of the app.Type: ApplicationFiled: July 23, 2021Publication date: January 26, 2023Applicant: Dell Products L.P.Inventors: Mohit ARORA, Danilo O. TAN, Zheng Yuan
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Publication number: 20230022048Abstract: Systems and methods for coalescing and/or aligning publications in a publication/subscription architecture to reduce the number of publication events and to improve the performance of microservices in a communications network are provided. A method, according to one implementation, includes the step of obtaining client-based tolerance input with respect to a plurality of subscriptions requested by a plurality of clients in a publication/subscription system. Based on the client-based tolerance input, the method also includes the step of adjusting the timing of publications to reduce the phase variability of the plurality of subscriptions.Type: ApplicationFiled: September 3, 2021Publication date: January 26, 2023Inventors: David Miedema, Amit Kumar Pandey, Kapil Rastogi, Mohit Arora
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Patent number: 11551769Abstract: A one-time programmable (OTP) memory has a plurality of pages. A predefined section of each page is configured to store error policy bits. When an indicator in a first predefined location has a first value, the page is configured to store data with error correction code (ECC) bits, and when the indicator has a second value, at least a portion of the page is configured to store data with redundancy. Address translation circuitry is configured to, in response to receiving an access address, use a second predefined location of an accessed page of the plurality of pages accessed by the access address to determine a physical address in the accessed page which corresponds to the access address.Type: GrantFiled: June 7, 2018Date of Patent: January 10, 2023Assignee: NXP USA, Inc.Inventors: Rakesh Pandey, Mohit Arora, Jun Xie
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Publication number: 20220374279Abstract: An integrated circuit includes a primary initiator domain (ID) circuit including having a processor core, a responder domain (RD) control circuit, and a reset controller. Secondary ID circuits, each include a processor core and a reset controller. RD circuitry is coupled to communicate with the primary ID circuit and the secondary ID circuits and includes RD resource circuits. The RD control circuit is configured to allocate each of the RD resource circuits to a first initiator domain consisting of the primary ID circuit or one of the secondary ID circuits, and when one of the secondary ID circuits enters a reset mode of operation, the RD resource circuit allocated to the one of the secondary ID circuits enters a reset while the remaining RD resource circuits are not affected by the reset.Type: ApplicationFiled: May 24, 2021Publication date: November 24, 2022Inventors: Mohit Arora, Milton Hissasi Kataoka, Marcos da Costa Barros, Tuongvu Van Nguyen, Rob Cosaro
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Publication number: 20220329405Abstract: A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.Type: ApplicationFiled: September 9, 2021Publication date: October 13, 2022Inventors: Nageswara Rao Kunchapu, Tamal Das, Akshay Karkal Kamath, Mohit Arora
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Publication number: 20220308554Abstract: A method for automatically scaling a number of robots leveraging interactive sessions to be used within a system infrastructure, dynamically based on workload, is provided. The method includes: receiving a request for a number of robots to be provisioned within the system infrastructure; validating an availability of the requested number of robots; monitoring a CPU utilization and a memory utilization within the system infrastructure; adjusting the requested number of robots based on the CPU utilization and/or the memory utilization; and releasing the adjusted number of robots for facilitating use thereof to perform corresponding tasks within the system infrastructure.Type: ApplicationFiled: March 24, 2021Publication date: September 29, 2022Applicant: JPMorgan Chase Bank, N.A.Inventors: Mohit ARORA, Rajeev SALARIA, Sanjay VENKITTAN, Ravi KAPPAGANTU
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Patent number: 11366488Abstract: An integrated circuit includes a first processing domain configured to run a first operating system and a second processing domain configured to run a second operating system that is different than the first operating system. The integrated circuit further includes a time stamp timer circuit in the first processing domain configured to provide a first time stamp value to the first processing domain and an adjusted second time stamp value to the second processing domain. The time stamp timer circuit includes a timer adjust circuit configured to synchronize the adjusted second time stamp value when a power up signal is received by the time stamp timer circuit from the second processing domain.Type: GrantFiled: May 20, 2021Date of Patent: June 21, 2022Assignee: NXP USA, Inc.Inventors: Mohit Arora, Tuongvu Van Nguyen, Milton Hissasi Kataoka, Rob Cosaro, Shenwei Wang