Abstract: According to one implementation of the present disclosure, a method includes determining one or more of a read current threshold, a leakage current threshold or a minimum assist voltage threshold; identifying a logic design, wherein the logic design is based the on one or more of the read current threshold, the leakage current threshold, or the minimum assist voltage threshold; identifying a bitcell-type and a corresponding version of the bitcell-type, wherein each version of the bitcell-type is associated with performance and power attributes of a bitcell of a memory array; and determining a memory optimization mode based on the identified logic design and the identified version of the bitcell-type.

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The wordline driver may include multiple transistors. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. Gates of the read assist transistor and at least one transistor of the multiple transistors may be coupled together. While activated, the read assist transistor may provide a read assist signal to the wordline when the wordline is selected and driven by the wordline driver.

Abstract: Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The wordline driver may include multiple transistors. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. Gates of the read assist transistor and at least one transistor of the multiple transistors may be coupled together. While activated, the read assist transistor may provide a read assist signal to the wordline when the wordline is selected and driven by the wordline driver.

Abstract: Disclosed are methods, systems and devices for operation of a circuit to boost a voltage at a load for a particular duration. A plurality of capacitors, each capacitor comprising at least a first terminal, may be coupled to an assisted node. At least a first capacitor and a second capacitor of the plurality of capacitors may maintain the assisted node at or about a target voltage for a duration. The second capacitor may be charged while the first capacitor is discharging in at least a portion of the duration.

Abstract: Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. The device may include a pair of write drivers coupled to the memory cell via the complementary bitlines. The pair of write drivers may be arranged to provide the complementary bitline signals to the memory cell based on complementary boost signals. The device may include a pair of complementary boost generators coupled to corresponding gates of the pair of write drivers. The pair of complementary boost generators may be arranged to selectively provide the complementary boost signals to the corresponding gates of the pair of write drivers based on the at least one data bit value.

Abstract: Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. The device may include a pair of write drivers coupled to the memory cell via the complementary bitlines. The pair of write drivers may be arranged to provide the complementary bitline signals to the memory cell based on complementary boost signals. The device may include a pair of complementary boost generators coupled to corresponding gates of the pair of write drivers. The pair of complementary boost generators may be arranged to selectively provide the complementary boost signals to the corresponding gates of the pair of write drivers based on the at least one data bit value.