Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A transmitting device generates an address field in a datagram, sets a value of at least one bit in the address field to indicate a number of bytes of data associated with a data frame of the datagram, generates the data frame in the datagram, the data frame including the number of bytes of data, and sends the datagram to a receiving device. A receiving device receives a datagram from a transmitting device, decodes an address field of the datagram to detect a number of bytes of data included in a data frame of the datagram based on a value of at least one bit in the address field, and decodes the data frame to recover the detected number of bytes of data.

Abstract: Systems, methods, and apparatus for communicating datagrams over a serial communication link are provided. A receiving device captures a sending device address during bus arbitration and receives a datagram subsequent to the bus arbitration. The datagram includes at least a register address and a payload. The receiving device obtains an address region specific to the sending device within a register space of the receiving device based on the captured sending device address and the register address included in the datagram and writes the payload of the datagram to the register space according to the obtained address region.

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link. A method performed at a transmitting device coupled to a communication link includes maintaining in a first register, a plurality of virtual general-purpose input/output (VGPIO) bits representing state of a one or more output GPIO pins at least one bit representative of state of an input GPIO pin of the first device, receiving first VGPIO state information directed to the first register, writing or refraining from writing a first set of bits of the first VGPIO state information to the first register based on the value of corresponding bits of a second register. The second set of bits may be directed to the one or more bits representative of state of output GPIO pins.

Abstract: A virtual GPIO architecture for an integrated circuit is provided that both serializesvirtual GPIO signals and deserializes virtual GPIO signals without the need for an external clock.

Abstract: A finite state machine is provided that both serializes virtual GPIO signals and messaging signals and that deserializer virtual GPIO signals and the messaging signals. The finite state machine frames the serialized virtual GPIO signals and messaging signals into frames each demarcated by a start bit and an end bit.

Abstract: A finite state machine is provided that both serializes virtual GPIO signals and messaging signals and that deserializer virtual GPIO signals and the messaging signals. The finite state machine frames the serialized virtual GPIO signals and messaging signals into frames each demarcated by a start bit and an end bit.

Abstract: A virtual GPIO architecture for an integrated circuit is provided that both serializes virtual GPIO signals and deserializes virtual GPIO signals without the need for an external clock.

Abstract: A RAKE receiver for use in a CDMA system is implemented as a transverse correlator in the complex domain. The transverse topology results in the correlator comprising a plurality of serial stages, each stage formed as a canonical unit of a multiplier, adder and memory. When implemented in the complex domain, the multiplier is replaced by multiplexers and the hardware may be significantly reduced by multiplexing between the I and Q components.

Abstract: An apparatus and a technique for adapting a plurality of tap weights in an adaptive filter where tap weights are adapted utilizing every other sample of a sequence of samples. The apparatus comprises a sampler circuit for sampling an input signal producing a sequence of samples; a tap weight processor for generating the plurality of tap weights coupled to the sampler circuit; wherein the plurality of tap weights are adapted utilizing every other sample of the sequence of samples.

Abstract: There is disclosed a loop counter reload circuit loads an initial count value into a counter and a shadow register. A count value output from the counter is changed by a predetermined displacement resulting in a changed count value. The count value from the shadow register is loaded into the counter if the changed count value has reached a predetermined reference value, and otherwise the changed count value is loaded into the counter.

Abstract: In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a sign detector adapted to determine whether a sum of an address pointer and a precomputed comparison term is of a first state or a second state. A first adder adds an address pointer and a precomputed correction term to generate a first potential next address pointer. A second adder, operating in parallel with the first adder, adds the address pointer and a displacement to generate a second potential next address pointer. A selector adapted to select the first potential next address pointer as an output when the sign detector output and a sign bit of the displacement are different, and to select the second potential next address pointer as an output when the sign detector output and a sign bit of the displacement are the same.

Abstract: In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative of one greater than an ending address, a second input that is a beginning address, and a select input that is the sign of a displacement for stepping through addresses in a circular buffer. The first selector is adapted to select one of its inputs as an output. A carry-save adder adapted to receive as inputs an inverted representation of the first selector output, an address pointer, and a displacement. The carry-save adder is adapted to add the inputs to produce sum bits and carry bits as outputs. A sign detector adapted to determine whether a sum of the sum bits and carry bits is greater than or equal to zero, or less than zero, and for providing an output indicative of whether the sum is greater than or equal to zero, or less than zero.

Abstract: In accordance with the present invention, an address arithmetic unit provides a modulo addressing technique for addressing memory locations in a circular buffer. The address arithmetic unit includes a first selector adapted to receive as a first input a value representative of one greater than an ending address, a second input that is a beginning address, and a select input that is the sign of a displacement for stepping through addresses in a circular buffer. The first selector is adapted to select one of its inputs as an output. A first adder combines an address pointer and displacement to produce a first potential next address pointer. A second adder combines the address pointer, the displacement, and a length modified by the sign of the displacement to produce a second potential next address pointer.