Abstract: Power management circuitry includes a power management circuitry having a handshake watchdog (HWD) timer and configured to, upon a reset, set the HWD timer to a maximum delay time allowed between an initial wakeup request received at a first input and a qualified wakeup request expected at a second input and configured to start the HWD timer counting in response to the initial wakeup request. Processing circuitry includes a wakeup signal aggregator configured to receive wakeup signals from internal and external wakeup events and to provide a notification of an occurrence of a wakeup event. The notification is provided as the initial wakeup request. A low power mode sequencer configured to initiate a low power mode exit sequence in response to the notification from the wakeup signal aggregator and to provide the qualified wakeup request as a result of performing at least a portion of the exit sequence.

Abstract: A host data processing system method, apparatus, and architecture are provided for sharing a PCIe EP device with one or more lendee data processing systems in a PCIe cluster by extracting an RID value from a received PCIe transaction message corresponding to a PCIe function at the PCIe endpoint device, and then processing the RID value to identify an interconnect target port value which corresponds to a first lendee data processing system which is sharing the PCIe endpoint device, and then routing the PCIe transaction message through an interconnect on the host data processing system using an interconnect target output port corresponding to the first interconnect target port value to deliver the PCIe transaction message to the first lendee data processing system.

Abstract: Facilitating access to a PCIe configuration space of a PCIe function associated with a computer comprises receiving by a PCIe controller EP in the computer over a PCIe link a configuration request from a remote computer to access a PCIe configuration space. The PCIe controller then communicates over a communication fabric the configuration request to a dispatcher of the computer. The dispatcher determines from the configuration request, a PCIe function and operation indicated in the configuration request which is used to identify a respective subsystem to execute the configuration request and the configuration request is communicated to the respective subsystem based on the identification. The subsystem then executes the configuration request to facilitate access to the PCIe configuration space of the PCIe function by the remote computer and sharing of the PCIe function with the remote computer.

Abstract: Processing circuitry includes a selectively powered domain having a communications interface to communicate with power management circuitry via a bus in accordance with a bus protocol, and a processing core to control the communications interface, wherein the selectively powered domain is not powered when the processing circuitry is operating in any one of multiple low power modes. The processing circuitry also includes an always on power domain having a set of pins to communicate a set of handshake signals with the power management circuitry and a power management sequencer to control power mode transitions of the processing circuitry. When the processing circuitry is operating in one of the multiple low power modes such that the communications interface and the processing core are not powered, the power management sequencer generates a signature on the set of handshake signals to control power mode transitions from one of the multiple low power modes.

Abstract: A host data processing system method, apparatus, and architecture are provided for sharing a PCIe EP device with one or more lendee data processing systems in a PCIe cluster by extracting an RID value from a received PCIe transaction message corresponding to a PCIe function at the PCIe endpoint device, and then processing the RID value to identify an interconnect target port value which corresponds to a first lendee data processing system which is sharing the PCIe endpoint device, and then routing the PCIe transaction message through an interconnect on the host data processing system using an interconnect target output port corresponding to the first interconnect target port value to deliver the PCIe transaction message to the first lendee data processing system.

Abstract: A system comprising a real time clock, RTC, and a processor configured to execute a secure application to provide a secure clock and configured to operate in a first low-power-mode and a first normal-mode, and a non-secure application configured to perform a clock modification procedure and configured to operate in a second low-power-mode and a second normal-mode, the system configured to perform a secure clock initialisation procedure comprising obtaining a record of a current time from the RTC based on a transition from the first low-power-mode to the first normal-mode, wherein the secure application is configured to perform a clock update procedure including updating the RTC with a secure record of the current time and wherein the system is further configured to prevent performing the clock modification procedure after the clock update procedure has been performed.

Abstract: Power management circuitry includes a power management circuitry having a handshake watchdog (HWD) timer and configured to, upon a reset, set the HWD timer to a maximum delay time allowed between an initial wakeup request received at a first input and a qualified wakeup request expected at a second input and configured to start the HWD timer counting in response to the initial wakeup request. Processing circuitry includes a wakeup signal aggregator configured to receive wakeup signals from internal and external wakeup events and to provide a notification of an occurrence of a wakeup event. The notification is provided as the initial wakeup request. A low power mode sequencer configured to initiate a low power mode exit sequence in response to the notification from the wakeup signal aggregator and to provide the qualified wakeup request as a result of performing at least a portion of the exit sequence.

Abstract: A method and apparatus for storing and classifying packets transmitted over a network to a processor in a low power mode. The processor receives and classifies the packets as interesting or not interesting. Uninteresting packets are discarded while interesting packets are stored in memory. For the first interesting packet received, a receive timer is activated and for every interesting packet received a counter is incremented. A transmit timer is activated when the processor enters the low power mode. When either the receive timer expires, the transmit timer expires or the counter reaches a threshold value then a wake-up interrupt is asserted.

Abstract: A method and apparatus for storing and classifying packets transmitted over a network to a processor in a low power mode. The processor receives and classifies the packets as interesting or not interesting. Uninteresting packets are discarded while interesting packets are stored in memory. For the first interesting packet received, a receive timer is activated and for every interesting packet received a counter is incremented. A transmit timer is activated when the processor enters the low power mode. When either the receive timer expires, the transmit timer expires or the counter reaches a threshold value then a wake-up interrupt is asserted.